Frequency sweep with constant signal delay

The traditional way of doing this is with a frequency of some multiple of the final frequency, and using a digital divider chain to generate the different phases. Using ring counters for the dividers may automatically give you the raw outputs you need. More generically called a "overlapping phase clock generator".

Another approach is phase-locked loops to ensure phasing between two oscillatorsbut for a 1kHz to 1MHz range you'd probably need several C's switched in and out of the oscillator/loop filters. Doing it all digitally is such a win.

Tim.

I can't imagine why not.

T00: S1 high T45: S1 low T55: S2 high T90: S2 Low repeat (T100 => T00')

And clock that at from 100 KHz to 100 MHz. Nothin' to it! You could even divide by five by hand first, to bring the clock down to 20 KHz to 20 MHz. It's a walk in the park! ;-)

Cheers! Rich

I agree that this will be easier to accomplish with digital circuitry but I cannot visualize the circuit that you guys are talking about. Would it not be possible to use a counter with state detection to toggle two different flip-flops (S1 & S2) at the proper times?

Yes, that's exactly what I was suggesting.

I wish you googlegroupies would learn to cut and paste some context.

Good Luck! Rich

Yes. Another way would be to use a chip like the HC4017.

It is a counter/decoder. It also outputs a signal that goes high when it wraps to 0. If you clock it at 20x your target frequency, you have signals which correspond to 5% of the intended period. Using a D flipflop, configured in the standard clock-toggle configuration, you can differentiate between the first and second 1/2 of the target period using that 'wrap' signal. Now, it is just a matter of 'or'ing the proper outputs of the 4017 for each signal, and 'and'ing the result with the output of the flipflop, and you can achieve waveforms like you require.

You can use wire-or with diodes to decrease the part-count, but it'll affect the accuracy of the output, particularly at the highest frequency you need.

Make sure all the logic you use is fast enough.

In article , Bob Monsen wrote: [....]

Better yet:

Run the outputs of the CD4017 to the J and K inputs on some flip-flops. The flip-flop's output will go high on the clock after its J goes high and low on the one just after its K goes high.

The advantage is that there can't be a race condition created glitch on the output like there could be with the OR gate method.

Yes, that is better. There is still some logic required to select the first or second half period. Perhaps a reset or an enable pin on the JKs could be used for this.