Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Please help me fast !!!!!
I need some vhdl code to configure a xupv2p board and how I'm supose to do the implementation part.
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16 years ago
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ise9.1i regid not working on x64
..but working fine using 32bit install (bin/nt/setup.exe of the DVD). Anyone have (or have a solution to) this problem?
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16 years ago
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DDR2 with Spartan-3A anybody having success??
an unhappy owner of the fresh new Spartan-3A development kit from Xilinx: reason for unhappiness: 1) NO examples how to use DDR2 IP core with Spartan3A 2) NO EDK reference design for this board at all...
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16 years ago
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weird PACE Error, not one google result
I get the following error in PACE after starting "Assign Package Pins" in ISE 9.1 SP3: ERROR:HDLParsers:3562 - line 1 Expecting 'vhdl' or 'verilog' keyword, found 'work'. It happens with a clean new...
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16 years ago
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Xilinx software quality - how low can it go ?!
Hi I really dont understand why Xilinx isnt hiring people who can develop and test software? Is the world-wide shortage of engineers really that bad? Latest example: MicroBlaze Working Design with EDK...
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16 years ago
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SAE j1850 pwm protocol controller ip core
hi all, can any one send me information about SAE j1850 pwm protocol i get free verilog or vhdl sources or free ip core any where. i have seen j1850 pwm BDLC controller data sheet by drivven software....
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16 years ago
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Serial FPDP
Hi, Does anyone have details regarding the sFPDP protocol and its implementation? Would be very grateful for any info. I have the doc from VITA, but not much given in there.
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16 years ago
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DS18B20 connection on FPGA?
Hello all. I'm new to FPGA and I need a little help with connecting Dallas 1-wire temperture DS18B20 sensor. I used that sensor many times with ARM and AVR MCU but never with FPGA. What I want to know...
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16 years ago
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Macro modified after Map ?
Hi I manually made one MACRO (.nmc file), in V2P30, ISE 8.2.03, for 16-bit AND function using 8 slices. Every LUT was manually programmed by "A1 * A2" Strangely, after place and route (PAR), I observe...
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16 years ago
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Interconnect architectures : Aurora and SPI-S
I was wondering if anyone had considered the possibility that the new OIF SPI-S using CEI 11G links may be compatible with and thus capable of enhancing Xilinx's current Aurora mesh-based architecture...
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16 years ago
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CMUcam2 and a XUP-V2Pro
Greetings all, Has anyone connected and used a CMUcam2 to a Digilent XUP-V2Pro FPGA board? If so, how did you do it? That is what module or connector did you use? I am trying to use the Uart lite IP...
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16 years ago
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driving Spartan-3 input from 74LS TTL
I've read answer record 19146 about using a series resistor for 5V tolerance on Spartan 3 inputs. If the signal source is a 74LS TTL signal (e.g., 74LS14), what is the maximum Voh I can expect (over...
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16 years ago
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fast arbiters (was Re: How to design an abitration cicuit...)
This is the way I make arbiters: // Concise priority arbiter input [26:0] req; // Bit zero is highest priority wire [26:0] gnt = req & -req; // Isolate least significant set bit Since this method uses...
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16 years ago
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How many Xilinx devkits does one need?
Hi I do have have plenty of Xilinx development hardware. I did thinkt hat for sure enough that i can pick up some board for almost any task. Now I just wanted to check out the Xilinx standard...
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16 years ago
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TigerSHARC TS201 to PLX 9656
Hi, Has anyone tried bridging the TS201 TigerSHARC with the PLX 9656 device? I'm trying to implement this in a current project and need details. The bridging is done via an Altera FPGA which also has...
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16 years ago
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