Now I follow... The key question is: can you generate (eg) a 4 Phase clock, from a
200MHz source, to give 4 phases each 90' apart (1.25ns), with a time-precision of +/-100ps on each edge ?I believe you can do this with the std DCM (so do not need a Cypress Clock chip?), but Peter A. might be able to better advise the Family/speed grade to do this ?
Since I think you want a pulse-modulation from this finer-time scheme, you will need to add the delay skews of the logic that decides which edge to act on. There is an Altera app note that specified the delays in each path of their LUT, and they are NOT all the same. Xilinx quote a single larger value, but it's not clear if that is because they are actually tightly matched, or if their SW cannot track the path deltas, so they take the worst one.
-jg