"bitness" is a silly category for processors. Databus width certainly does affect performance. Does a processor with a maximum system clock rate of X, that requires doubling up the databus accesses because of "mini-bitness" sizes mean it performs the same as a different processor family at rate X that has the same databus "bitness" as its internal registers/ALU? Or even the exact same processor family; model Y of system clock rate X and databus of "half bitness" versus model Y2 of system clock rate X and databus of "full bitness". Of course not. But a better metric is a processor's Dhrystone results. Would you suggest that a processor with a half-databus compared with its "bitness" per your definition, would chunk out the same Dhrystone as the exact same processor architecture, model 2, with the same bitness of databus? If you do, *that* is ridiculous. "bitness" is marketing fluff. So let us not take up anymore comp.arch.embedded database space with this discussion thread; especially of the server supporting the database is running a "half bitness" processor ;)
********************************************* Jeff