1. Home
  2. Embedded Programming
  3. Lan91C111 PHY problem

Lan91C111 PHY problem

Hi

First let me start by describing the hardware that I am using. I am using the SMSC LAN91C111 ethernet MAC & PHY which is driven by the Renesas 7144F processor (16-bit interface). I am not using a EEPROM in conjunction with the SMSC device hence the EEPEN pin is tied low and the IOS0-2 pins are left floating. Furthermore RBIAS is tied via a 11K resistor to ground.

As the hardware stands at present, I am able to write and read data to the MAC correctly. This has been verified for all 4 reg banks of the MAC. What is strange is that I cannot seem to access the PHY in any way whatsoever. I am using the MGNT reg in bank 3 and clocking the data as described in the data sheet by starting with 32 1's etc etc.

Obvioulsy you cannot tell what is going on in the chip so I then set the SMSC to external PHY. By doing so, I was able to see the data being clocked correctly out on the MDO pin as well as the MCLK pin toggling. I then set the device to use the internal PHY once again but alas no luck! It just seems dead. The only data that I get is a series of: 0x0000

The data sheet doesn't mention what the maximum speed for communicating with the PHY is. Can anyone shed some light on this? Also, does anyone have any other suggestions for me to try as I am now starting to get desperate? I have looked at the SMSC trouble shooting FAQ and have ensured that all the bits are set/cleared correctly as recommended in order to solve this type of problem. Still no luck though.

Please help if you can!

Many thanks Ryan

Reply to
Ryan
Loading thread data ...

I have what is probably a very similar system, using the 7017 processor which IIRC is basically a 7044 (the 5V version of the 7144 with a DRAM Interface) that is forced to have a 16 bit bus by the package only bringing ot the 16 low bits of the data bus.

I also don't have a serial EEPROM and am loading the MACID via the registers and it is currently working without any problems.

I don't have all the information here and I won't be able to check until Thurs but I don't remember adding any delays clocking the Phy using the MGMT reg with a 28MHz CPU clock. I do remember something about the internal PHY address being different to the data sheet.

I'll try to get back to you sometime on Thursday (US EST).

Stan

Reply to
Stan Katz

I have a phyCore2294 + 91C111 (LPC2294) with an 8bit bus. I _can_ read/write the Phy registers but I can not set the Phy to

100MB.

Most of the sources I saw insert 50us delay after writing the data and another after setting the clk to 1.

What do you get when reading Phy register 2 and 3 ? Should be 0x16f84x (last digit may vary).

My first attempts gave me a value shifted one left.

--
42Bastian
Do not email to bastian42@yahoo.com, it's a spam-only account :-)
Use @epost.de instead !
Reply to
42Bastian Schick

I had the exact same symptoms. The cause was Analog ground (connected to LAN91C111 AVSS pins) not being tied to Digital ground (connected to VSS pins).

Cheers TW

Reply to
Ted Wood

Hello

to

What I do is to read the management interface register, clear out the MDOE, MCLK, MDI and MDO. Then for reach bit in the MII frame I set the MDO bit as it needs to be (0 or 1) and write that back to the management interface register...wait about 1 ms...then I write the same value again to the management interface register, this time with MCLK set to 1....wait about 1 ms again...then read the management interface register again, pull the MDI from it and shift it appropriately, ignoring the MDI until we are at the read back portion of the sequence of course.

now

I used a 1 millisecond delay between each write to the management interface register which is probably overkill but since I only tweak the PHY myself at boot time, an extra 20 or 30 milliseconds is not noticed in my product.

Somewhere in the datasheet there is an MII example, have you tried sending that EXACT frame to the PHY and see what you get? When I first wrote my driver I had screwed up the MII register address and got all

0's back.

Good luck!

Ben

Reply to
Benjamin M. Stocks

Hi

I want to just thank all the people that replied to my questions about the Lan91C111 PHY problem. As Ted suggested in the last reply, I was experiencing a problem with the AVSS pins. After attaching them to the common ground, the phy worked like a dream.

Once again, thanks for al your help!

Ryan

Reply to
Ryan

Replying myself :( Well, I just heard my problem is related to the hardware (Phytec phyCore2294 + base board, the base board seems to have a problem, not the cpu board).

--
42Bastian
Do not email to bastian42@yahoo.com, it's a spam-only account :-)
Use @epost.de instead !
Reply to
42Bastian Schick

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.