Hi,
In M16c, after a peripheral interrupt was disabled by setting it's interrupt control register's LVL bits to 0, and then the interrupt just comes in, and after a while the interrupt was enabled by setting the LVL to a value other than 0. I want to ask, in this time, will the ISR be invoked? Put it this way: Will a peripheral interrupt keep pending while it is disabled?
Thanks.
Would anyone like to answer the question? Thanks
AFAIK yes, the interrupt request bit remains 1 once the interrupt condition occurred. Have a look on chapter 24.7.6 (Precautions/ Interrupt/ Rewrite the Interrupt Control Register) inside the m16c manual. Having not done this I got spurios interrupts which gave me quite a headache. Regards Dirk
It may depend on the peripheral. If the interrupt condition occurs and you do not clear it before changing the LVL bits, then it will probably still get the interrupt. From the manul it looks like the interrupts are edge triggered. If that is the case then you will not get the interrupt. There are lots of information about rerwriting the interrupt registers in the manual.
Read chapter 4 of the M16C users manual.
Scott
What you mean by 'the interrupts are edge triggered'? Thank you .
Interrupts are detected in one of two ways, they are either edge-triggered or level sensitive. Level sensitive means that the interrupt is detected by the static state of the signal line. Edge-triggered means that the interrupt is triggered by a transition on the signal line. The static state of the signal is irrelevent.
Think of edge-triggered as being like a clock to a latch. Only the transistion is important. If you miss the transition then you miss the interrupt.
Scott
keep
Before you alter the LVL bits in the Interrupt Control register, you should disable all interrupts and clear Interrupt Request bit. You can then enable interrupts to allow anything that "happened" while you were modifying the registers to be serviced.
You may also want to try posting this question to Renesasrulz.com
Thanks for the explain. The interrupt under my question is edge- triggered. I need to set the interrupt control register's POL bit before receive the next interrupt. But one thing I don't understand, when an edge-triggerred interrupt comes in, the CPU should know the requst and the Interrupt Request (IR) bit of the interrupt control register should set to 1. So, after a while when the interrupt was enabled (setting it's interrupt priority level back to normal), the CPU should be able to acknowledge the pasted interrupt and begin the interrupt sequence. Is my understanding right? I just don't know if or not the M16C will do its job like this way.
Thank you so much, Vinnie!
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