msp430 interrupt question

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Here are the situations.  

1. Say I have an interrupt service routine which triggers off an
interrupt of lowest priority, and during this routine the other lowest
priority (but still equal priority) interrupt occurs, will this state
be stored? so that once the RTI has occurred in the original service
routine, will the next interrupt be handled or cleared?

2.  In a similar situation a lower priority interrupt has occurred but
then a higher one occurs but the mask bit of the higher one is set.
Once the ISR has been completed and the mask bit cleared but the
source of the interrupt (the higher one) is gone, will there still be
information stored somewhere that this did occur ? sort of a stack for
interrupts ?


Re: msp430 interrupt question

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Probably.  In most microcontrollers, the interrupt event sets an
interrupt flag that remains set until it is cleared.  On some micros
you have to take software action to clear the flag (in the code).  In
others, the flag is cleared automatically when the interrupt vector is
fetched.  In either case, if an interrupt flag is set when interrupts
are enabled, the interrupt service routine is invoked.  Check your
data sheet to be sure.

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This seems to be the same question.  Or am I mis-reading?

When an ISR is invoked, interrupts are disabled.  So unless the ISR
explicitly enables them, it won't be interrupted, even by a
higher-priority interrupt.  The new interrupt won't be serviced until
the current ISR enables interrupts or returns.

If the lower-priority interrupt does enable interrupts and is
interrupted, the higher-priority ISR will return to the location from
which it was invoked -- the lower priority ISR.


Change is inevitable, progress is not.

Re: msp430 interrupt question

You have essentially asked the same question twice.
With the 430 (as with all other Micro's I've seen) you cannot have any
interrupt of equal priority. If the logic of the micro has to make a
decision between 2 or more interrupts that have been flagged, it must make a
prioritized response.

Each interrupt is flagged and remains so until it has been serviced and

However, this is only true for different interrupt sources, eg uart, timer,
ATD etc. If however, other interrupt requests of the same type occur before
the already flagged request has been serviced, they will be lost. For eg a
timer interrupt is set to occur every mS. The timer interrupt flag gets set
after the first mS and it is not serviced within the next mS, the second
interrupt request will go un-noted as there is only one flag.

So in short, Yes the interrupts are "stacked" but only one each.

Hope it helps


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Re: msp430 interrupt question
There is are simple answers to both questions.

Interrupts are flagged whether they are enabled or not. Thus your ISR
that enables the interrupt must also clear the pending flag, other wise
you could be responding to an interrupt that occurred weeks ago. Put
another way, as soon as you enable a maskable interrupt it will be
serviced once global interrupts are enabled if the interrupt flag is
set. That flag can be set regardless of the IE bit.

Some interrupts have many sources. For example the TimerA_1 & 2
interrupts and the TimerB_1-6 interrupts share an interrupt vector, but,
because they have individual flags in their respective control registers
they can occur in 'parallel', so that the ISR for these can be called
sequentially. Interrupts won't be lost. However, in the case of a
multiple source interrupt that has only a single flag, such as the A/d
converter. It may be possible, with some configurations to lose an
interrupt that occurs while that ISR is processing, and before the ISR
clears the related flag. All single source, and multiple source,
multiple flag interrupts also have this potential. Ie the same interrupt
cannot re-occur until it has been serviced and the flag bit cleared.
there is no flag buffering.

The MSP430 is very robust in this respect. There are very few situations
that might result in a 'lost' interrupt given that normal care is taken
with ISR design.


Don wrote:
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