If CPU is servicing a pin 5 interrupt in ISR, and there is another interrupt pin 3 (with higher priority) comes in. Will CPU stops servicing a pin 5 interrupt and handles interrupt pin 3 first? Or it will wait until pin 5 ISR is done?
please advice. thanks...
This group should be renamed comp.arch.clairvoyant.
Seeing as my powers are week today - which processor are you talking about?
Regards, Richard.
There's no way to tell if you don't tell us what CPU you are using.
And how it's configured and what the ISR for pin 5 does.
Given that you haven't seen fit to tell us what processor you're using I'll make some general statements:
Most processors that have prioritized interrupt schemes still turn off all interrupts when an ISR is entered. Unless you do something specific to turn interrupts back on the second interrupt will most likely pend until the first ISR returns (most processors' return-from-interrupt instructions also restore the interrupt state).
To actually find out what happens on your mystery machine, you'll have to look in the manuals. "Nest" is the key word, from "nested interrupts" or "interrupt nesting".
Yes
As a rule, yes - that's what prioritised interrupts means; a higher priority interrupt can interrupt a currently running lower priority interrupt. Whether this behaviour can be modified depends on the particular processor you are using.
ian
In the PIC18 family of MCUs the low-priority ISR will be interrupted by the high-priority interrupt, the high-priority ISR will be executed completely, and then the low-priority ISR will resume. The high-priority ISR will not be interrupted by any interrupts. This is the default behaviour (no changes in the global interrupt enable flags GIEL/GIEH from within each ISR). You can achieve all sorts of nested interrupt scenarios if you play with these flags.
You'll need to let us know what processor you're referring to...
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