We are creating a device which is to be slave device on a RS-485 bus. Th protocol on the bus is not doumented and hence we are reverse engineerin as we are going.
The slave devices are configured unique addresses which can be upto bytes. The master periodically sends out what we call IDLE messages whic is a set of 4 bytes.
If a device wants access to the BUS it seems that the slave has to sen its address between the IDLE bytes such as:
I1 I2 I3 I4 > IDLE bytes from the Master F6 > from Salve to request bus
Then Master replies with a bus grant message and thereby Slave has th bus.
The problem: ============ On the analyzer we find that I1 and F6 start at the same time.
We are not sure how does Slave respond almost immediately when I1 i generated by the Master.
We also see E4 and E2 events on the BUS (which we currently do no understand) and believe that may the way I1 and F6 are synchronized.
Any ideas on how this may be done is appreciated.
Our hw is currently not available hence we are trying to simulate this o a Windows machine.