Hi, I'm having trouble figuring out how to architect a robust system using the FTDI chips in FIFO mode. I'm pretty sure some of you have been through this before.
I'm using the FT2232H in synchronous FIFO, but my concerns are general.
The system has PC FT2232H FPGA, and is used to both stream/receive data between the PC and the FPGA.
I'm wanting to stream continuous data at about 1MB/s each way, WHILE also sending various control commands to the FPGA (low rate).
Now the FPGA will have some kind of state-machine that reads data from the FTDI. It needs to decide if this 'data' is for streaming, or if it's a command to write to a register. I thought of building and sending a fixed 'packet', that always contain say 32 kBytes of streaming data, and 8kBytes of control, or some variant of this.
Now my concern is that there is no synchronization between the FPGA state machine and the FT2232H FIFO. If something goes wrong, the FPGA could start mixing the data.
I'm used to I2C, or SPI, where there is either a CLATCH event, or a START condition, that marks the beginning of a new transfer. Here, there is none of this.
Any idea?
Diego
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