Hi, I need to stream audio data and control info I2C out of my PC into some external hardware and was thinking of using a FIFO to deal with the different clock boundaries.
I was wondering if anyone had some startup verilog code on FIFOs, I am using a Xilinx FPGA
Thanks
Ryan ( snipped-for-privacy@gmail.com)
I've done just that using ALtera's tools except I used the graphical design as the input. So I placed a fifo set it width and depth. Then wraped controling logid arround it.
I then had the tools generate VHDL output.
I'm still using the graphical as the master but could switch when necessary.
George
I agree with "GMM50", don't waste your time writing your own FIFO. Pick one from the Xilinx library. They should have ready-made FIFOs available, if not then switch to Altera.
-JV
You may want to look at Xilinx application note 175, together with the zip archive containing the HDL code. It has both synchronous and asynchronous FIFOs ready to go.
DJ
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