Antti, I actually have something along those lines way back in my archives. Unfortunately, it was for an XC3100 series part and was done as a schematic using Viewlogic. I'd have to do some digging to a) find it, and b) extract it at this point. Unfortunately, I don't have the spare bandwidth to tackle that at the moment.
Re Quad Serial memory devices, and execute in place : I see SST have just released a Quad device as well. $1.16/10K for 16MBit
Good news, and bad news :
Good news: 80MHz nibble rate. They also added 8 & 16 bit address modes, to the default 24 bit. Bad News: These short-jump modes _are_ signed relative, BUT they do NOT cross page boundaries. (ie Just like the 8048...)
So, the idea falls short of being usable in relocatable code.
Pity, as a memory-opcode jump is a good way to save some bandwidth
Why make something signed relative, but then have it page-wrap ?
- was this a bug, maybe they intended it to work properly, but found an oops, and changed the data to match the silicon ?
-jg
I knew there was something fundamentally wrong with the idea of a very slow processor in an FPGA executing from an external memory chip. I figured out what it is. Using even *less* real estate inside the FPGA and by adding only two, very inexpensive chips, I can add an
*external* processor and (optionally) a serial memory chip to interface with the FPGA through a serial port such as SPI, I2C or custom. Rather than try to implement a full processor in minimal gates, isn't it easier and more effective to use a serial control to allow an external processor to control the FPGA, while matching the size and cost to the job?Even 32 bit flash based ARM chips are available for less than the cost of the serial memory.
;) I am doing myself exactly this A3P060 3.5 AT45DB161D 1.0 ATmega88 0.8 ========== ;)
but there is still room and need for low FPGA estate serial engine at least i think so
Antti
Yes, Of course; That's the litmus test ALL soft-CPU choices must face.
It is nearly always better to use a dedicated Microcontroller IF one is available that fits. (and mop the 'other stuff' up in the (now hopefully smaller) FPGA)
The range of dedicated controllers is also expanding all the time. Ethernet and USB are becoming small incremental adders.
I see the serial CPU as something more of a paper exercise, that 'defines the numbers' : How small can it be, and how slow ? What chips are out there, that support such a design ?
Quad-SPI devices are relatively new, and give another pincount/bandwidth design point.
FPGA vendors need to include them on their configuration memory support list, for faster config times.
SST claim they target Execute in place with their device. I've asked SST for some examples of that, and for examples of a design that actually uses their strange wraping-relative-jumps :)
-jg
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