I am always astounded by the lack of interest in component re-use as found in so many posts in this newsgroup; there are _scads_ of ISA VGA cards around in every berg on the planet and even in rural waste transfer stations; drive down any alley in a town of more than one stoplight and you are bound to find PCs which are likely to contain an ISA VGA card (8 or 16-bit useable in 8-bit mode). For a 'small volume' application coming up with even hundreds of ISA VGA cards should present less of a logistics problem than specifying some currently marketed solution. Our local metal recycler has a gaylord with at least that many at any given instant in time.
I agree this sounds doable, but I would not expect this system to work unless you are delivering at minimum VGA scanrates.
A method I used to drive an LCD (not DVI) "directly" from an 8051 was to embed the sync signal in spare RAM bits; i.e. I used two bits each for r,g,b in a x8 SRAM and put the v-sync and h-sync bits in the remaining bits. The v-sync bit caused a micro interrupt; the micro then held v-sync active while resetting the counter that addressed the video RAM. (Actually it was a bit more complex than this - the micro tristated the counter and held the v-sync active, then if necessary wiggled the address/data bus on the RAM to update display data).
Your intermediate divider and base dot clock will depend on what resolution you want to use to drive the display. You will probably also want to add extra logic so that you can reuse scanline data; i.e. have separate scanline and dot position counters and ignore the lower bits.
Let's try to work some nice numbers into this. Start with a 32kHz horz sync, since it's a nice round number. You need to supply a v-sync pulse every 480 lines, which is 15ms (66.67Hz).
Yes, it could. You could use a fast uC, and then a TS counter like the HC590, to clock the line pixels, and INT the uC at line ends, so the processor runs < line speeds. If you are ok with 256n clocks across the screen, then uC resource like the PCA in the SiLabs parts, would manage blanking and any resets needed. DRAM would be interesting, but perhaps not a very stable target.
Well I would first look at the manufacturers of the DVI (LVDS etc chips) for example National DS90CF383, they have a whole series of app notes on driving monitors using these sorts of interfaces.
The problems I have found with various LCDs/monitors that use a DVI or DVI style interface, they can go screwball if you miss one clock cycle or worst get one pixel difference between two frames. They tend to use Hsync Vsync and enable as helpers, and not resyncers as monitors do, so make sure you have the right amount of clock pulses on every line INCLUDING blanking.
Work out what scheme of bpp you want as well as encoding. Supply the parallel data to the LVDS or TMDS chip and timing and you are away.
Make sure the clock sent has the expected frequency for the display format even if you are using it a lower resolution, not all the rescalers are good at dcoding and expect exact frequencies and ratios.
Some displays will balk at that especially if they do not get a repeated frame in 40-60 Hz rate. LCD specs are notoriously at specifying min and max clock, Hsync, Vsync rates. they tend to spec at one display format only.
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Depending on your needs TV and teletext chips would be another option. Philips makes the SAA5x9x series, which is 8051 based, and some of these chips even allow external data and external program memory. These processors have video hardware inside, and instead of receiving teletext data you could write into the internal display ram in order to to display things. Some of these are also 100/120 hz ready.
The older chips (SAA1054 etc) were i2c controllable, without internal CPU. If you can still get them, they are easier to work with due to lower pincount.
You must feed an empty BAS signal (sync only) into these controllers for video timing.
That would be 'funny' if you were right but you are wrong as analog DVI interface for monitors exists. I suggest you read up on the matter as that is refered to as DVI-A connections.
The other references below refer to single link, compared to dual link for larger displays and alternate pixels on alternate links to reduce clock speeds.
DVI-D
DVI-I ....
The same as a monochrome RGB, making all channels the same, colour depends on the application driving the signals.
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used ones are easily had in small volumes, the hardware, if treated as VGA, should perform near identically across different brands if N of identical cards can't be found.
some of them want +/- 12V supplies which may be a hassle.
That would be an easy solution. The more I look into DVI the better a plain old 640x480 VGA looks. It might just turn out that displays with 15-pin VGA inputs will be available long after DVI is replaced by The Next New Thing.
Still, the idea of a fast-clocked counter clocking a DVI signal out of SRAM is appealing enough to where I will most likely breadboard one up and see how well it works.
...that said SRAM has it's address lines incremented by a counter (assume RD. WR. CS, etc are all taken care of properly).
...and that said counter can be reset to zero at any point you choose (not just powers of 2)
...
What frequency should the counter run at?
How many RAM addresses does it need to access?
How many bits wide should the RAM be?
At what number of bits should the counter be reset in order to start the next frame?
Hint: A single DVI link consists of four twisted pairs (red, green, blue, and clock) to transmit 8 bits for each 3 colors per pixel. All you need to do is add them up and then figure out how much, if any time is spent blanking and retrcacing. This should be a simple task for a display developer.
In front of me is a catalog that lists the following connectors:
DVI-A One set of eight pins and one set of four pins plush four contacts around the blade
DVI-D Single Link Two sets of nine pins with no contacts around the blade
DVI-D Dual Link One set of 24 pins with no contacts around the blade
DVI-I Single Link Two sets of nine pins plus four contacts around the blade
DVI-I Dual Link One set of 24 pins plus four contacts around the blade
More info from my looking into this (I have the flu, so forgive me if this is disjointed and/or wrong...):
formatting link
gives these figures:
1024 X 768 @ 60 Hz = 65 MHz Pixel clock.
formatting link
Gives me the following DVI-D pinout:
1 TMDS Data2-
2 TMDS Data2+
3 TMDS Data2/4 Shield
6 DDC Clock [SCL]
7 DDC Data [SDA]
8 Analog vertical sync
9 TMDS Data1-
10 TMDS Data1+
11 TMDS Data1/3 Shield
14 +5 V Power
15 Ground
16 Hot Plug Detect
17 TMDS Data0-
18 TMDSData0+
19 TMDS Data0/5 Shield
22 TMDS Clock Shield
23 TMDS Clock +
24 TMDS Clock -
4, 5, 12, 13, 20, 21 not used
DDC = Display Data Channel TMDS.= Transition Minimized Differential Signal
formatting link
(page 25 or so) talks about TMDS encoding. My next step is to get a good enough understanding of TMDS encoding to determine whether I can pre-encode before storing to SRAM or whether I need a post-SRAM hardware encoder. Or whether to give up and stick with VGA.
- assume no dead-time, and you get 60*768*1024 = ~47MHz (call that 50MHz). Ram width is up to you - 24bits wide = Pixel clock, 8 bits = 3x pixel clock. Plus you need to serialise if this is LVDS, so to serialise 8 bits digital onto 1 pair, is > 8x pixel clock = 2.5ns data slices
So to keep this sensible, you'd probably need x24 SRAM, and commercial SerDes encoder.
Check a recent device like
formatting link
targets links to LCDs in cellphones, (Wider fanin, but lower Fin than above numbers), has link clock of ~275MHz
As you know the A stands for ANALOG. The Analog portion of the DVI connector is a VGA signal set piggybacked on the DVI interface. There is no ANALOG-DIGITAL-VIDEO format. Nor is there any ANALOG - DIGITAL Anything format. When I am told there is a DVI signal in a system I never ask "Is it the Analog DVI?", cause I like my job.
You can find the timings for generating vga, svga, xga, sxga, uxga anywhere on the web.
The pixel clock for xga is 65 Mhz. Don't forget the inactive, non-displayed portions of the signal.
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