Augh! WTF 'megabaud'?

As far as I can tell, SPI means that there's a Clock line, a Data line, and a Strobe/ChipSelect somewhere nearby. Sometimes two data lines, in and out. I've seen "SPI" devices with bidirectional data, separate data, rising-edge clocks, falling-edge clocks, active-high select, active-low select, various logic levels, and all sorts of speed specs, up to 10's of MHz. If there are any rules, nobody seems to be following them.

John

You may be getting caught in the TLA duplication zone.

The SPI you want is the 'Serial Peripheral Interface', originally by Motorola (now either Freescale or OnSemi, depending on your parts). There's a useful tools called SPIGEN at

I have never found the definitive specification and simply used the timing diagrams from the 68332 family.

There's a different 'SPI' physical layer that refers to the SPI-x System Packet level Interface (currently SPI4-2). You can read about that here:

For SPI, (Mot style, anyway), you need MOSI (Master Out, Slave in), MISO, Clock.

Some devices also need Frame / CS (the device becomes an active participant during frame active).

Hope that helps

Cheers

PeteS

As John stated, it could be :)

I see your point though - Baud is perhaps the most misused term in communications I know of.

Cheers

PeteS

I love the 68332; I'm hacking a big assembly program right now.

The only thing you can do when you use an SPI-claimed serial device is read the datasheet *very carefully*. Being lucky doesn't hurt, either.

John

Yeah, it's right up there with "bandwidth" (when used to mean "data rate" or "channel capacity") and "resolution" (when used to refer to the number of pixels an image or display provides in "X x Y" numbers)....

Bob M.

Touche`. :-)

"A 'BAUD' IS NOT NECESSARILY A 'BIT PER SECOND'!"

Nah, just doesn't have the same 'Oomph!' to it. ;-P

...

LOL! Yeah, thanks for this. This is the conclusion I've been inexorably coming to - and I think that it doesn't even care if the clock is a nice, tidy, jitter-free pulse train - You put your zero on the CS, you put your data on MOSI, you put your one on "clock", you shift your data, lower the clock, count the bit, test, and if it isn't bit 8, shift and loop. Repeat for as many bytes as needed.

It's even sounding like I could bitbang it raw, and it wouldn't matter if it got interrupted. The slave would just be sitting there, waiting for the next clock, until the next clock.

Kewl! [OBTW - the task has evolved to PIC, which it's turning out is also kewl - MPLAB is free!

Yeah, that's the one. :-)

Yes, and I've been doing just that, against the day that I find out that I have to make up my own spec for my own design, based on meeting all of the other chips' worst-case setup and hold times. I'm not too worried about clock rate, bitbanging. :-)

Other than that, I get the distinct impression (from my studies and feedback) that I can do pretty much any thing I want to. >:->

With a 4 MHz clock, a reasonably well-written loop could maybe do

Just this afternoon we were discussing whether it was worth using the dedicated SPI interface in the 68332 to program a couple of Xilinx chips (essentially SPI in slave serial mode) or whether to just keep bit-banging like we usually do. We checked some old code and it looks like we're banging about 600 kbits/second, with a 20 MHz CPU clock. We copied (we call it "cached" to sound more professional) the code from eprom into CPU internal ram to speed things up, and the code is fairly tweaked assembly.

We're planning a product with maybe 10 mbits of Xilinx configuration data, 15 seconds or so to configure, so the hardware SPI thing starts to look interesting there.

Hey, if you had an fpga that was partially configurable, you could do a sort of bootstrap operation, serially load a small block that lets you parallel-load the rest.

John

Something I did not mention about 'SPI' is that it's sometimes called a Sync Serial Interface, and there are 3 variants at least:

Intel Style (single data line that gets turned around, but still uses the same overall protocol) National (almost like Mot) Mot style.

Take a look at this datasheet

It's a device I'm using in a design and around page 20 or so you get a choice of interface styles on the sync serial (command) port.

Cheers

PeteS

Thanks for this. I'm definitely feeling a lot more comfortable about just saying, "This is how my design outputs its SPI, and BTW here are the command strings it's going to be expecting from your Master Control Computer." I guess if I'm the designer, that is my job, after all. :-)

Thanks again! Rich

Well, I've still got custody of my client's Xilinx development board, but the project has gone micro - PIC16F627A, and I've downloaded MPLAB, which is also way cool.

But I look at that Xilinx IDE, and all of the libraries, and I salivate. You can do _ANYTHING_ with that chip! The development board ships with an 8-bit Johnson Counter already programmed into it. Chasing LEDs don't photograph well. :-) file:/home/richgrise/Pictures/100_fuji/dscf0307.jpg - no flash file:/home/richgrise/Pictures/100_fuji/dscf0308.jpg - with flash; you can just barely tell that the four lower LEDs are lit. :-)

Cheers! Rich

Exactly. We don't follow rules, we make rules.

John

I still have the full Xilinx ISE system on my computer, with all the libs. I had to do a major interface design and you're right - you can do *anything* with the things.

That beast had to interface from **6** PPC busses (although I had two busses per port as I had CS0/1 functionality on the targets) to a single synchronous bus and provide data / message buffering per channel, a priority interrupt controller and message handling by message type.

I love the Xilinx implementation of dual port RAMs - clean and easy to use. I must admit the internal address decoder was a large chunk of Verilog, to say nothing of the 7 picoblaze cores I instantiated ;)

The only problem I have had with FPGAs is cost - it has to replace a fairly major piece of hardware to be cost-effective (although playing Altera against Xilinx has been known to bring the proce down :> )

Cheers

PeteS