I've thought I had this particular matter planned out properly about two different times now, but when I look at 6502 timings in relation to my planned circuit already, I thought I'd ask to confirm.
Basically, I want to write to a latch (or well, a '374 octal flip-flop), which has a positive-triggered clock. I should point out that my decoding logic begins with a '139, using both O2 and A15 to determine whether we're trying to access the upper or lower 32k, and then I drill down from there. This means my latch /CE equivalent will only be active for as long as O2 is. O2 seems to go low around mid-way that the data lines are active, so this seems to be the best way to handle any chip enables. But, of course, I only watch the latch to grab data when the write signal is active as well, because later I'll possibly add in a tri-state buffer to be able to read its contents back out.
Anyhoo, so I figure if I invert both its /CE and the R/W signal, run them through an AND gate, then invert the output of the AND gate going into the clock of the latch (positive-triggered, remember), I *should* be able to clock the latch at the proper time to grab the data lines, since O2 goes low while the data lines are still active (and if O2 goes low, my /CE is disabled, and the latch clock input goes high, which should grab the current state of the data lines).
This is probably hard to digest with just my explanation of the process, but if it doesn't make a lot of sense, perhaps someone with a better knowledge of 6502 timings can simply share the "proper" way to clock a positive-triggered latch in order to write to it. Though if my blabbing does make sense, I'd be even happier to know if it should work properly. lol. But any help to verify my solution or give a better method would be much appreciated!