Winter School on Timing for Deep Submicron Chips, Cambridge, England, 3-7 January 2005

This Winter School will address how to mix synchronous and asynchronous techniques to build robust systems on chip. It is aimed at systems architects, VLSI designers and researchers.

Check out

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for further details and online registration. Register before 17 December

2004 --- limited to 50 participants.

The School is organized by the Working Group on Asynchronous Circuit Design (ACiD-WG) with funding from the European Commission.

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Prof. Mark B. Josephs
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