IDE/ATA-3 Timing Diagram

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Does anyone know where I can find a timing diagram of the ATA/IDE electrical
interface in various PIO modes?  I'm having some strange problems.  I've
found some specifications (in MS Word), but they do not include an actual
timing diagram so I'm guessing at how a couple of values are measured.  I'm
afraid I'm guessing wrong on a couple..


Re: IDE/ATA-3 Timing Diagram

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I grabbed a copy of the ATA Rev. 5 spec. from, it has the
timing diagrams with the table of times for each PIO and DMA mode.

- Mark ->

Re: IDE/ATA-3 Timing Diagram
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Pardon me for butting in, but I have a related question...

What about CF drives in memory-mapped mode? I've been playing with dozens of
different CF drives over the last year and can see no correlation between
bus timings in memory-mapped mode and PIO cycle times. In every case, I've
always has to code memory controller settings based on the manufacturer's
data sheets; the PIO mode in the CIS is no use what-so-ever. SanDisk have a
couple of drives now that get up to 10MB/s sustained, but to reach this one
has to set up memory controllers pretty specificaly; there is nothing in the
CIS that helps... as far as I can see. Does anyone have a solution?


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