Timing on PCB

There is no necessary trace length for data signals to memory. Signal transmission speeds are around 2/3 of the speed of light ( 1 foot per nanaosecond) on printed circuit board, which is rarely significant on all but the largest printed circuit boards, and then only with very fast logic.

You can slow down the propagation speed by loading the trace with a small capacitance at regular intervals - as on a bus - but this also messes up the edge speed, so it hardly ever comes into consideration. Microstrip transmission lines

on the surface of a printed circuit board are dispersive, so you don't want to make them too long. Buried stripline transmission lines - with ground planes above and below the signal trace - aren't dispersive

If you do need trace lengths, up-market printed circuit layout programs will calculate it for you - on the one occasion when I went to the trouble (on a board using ECLinPS logic) I had to add up segent lengths with my calculator. Very tedious, but Ultiboard 4.84 was cheap.

Don't I even have to consider timing on the curcuit board with SDRAM running on 150 MHz..? Don't I have to consider trace capacitance slowing down the signals different due to different trace lenghts?

Aren't the simuation programs mainly for signal "integrety" issues and not for timing..?

/CeeRox

You can figure this one out with a bit of maths. At 150 MHz, your clock periods are about 6 ns. In this time, the signal can travel 6*(2/3)*30 = 120 cm (about 4 ft in old money). Thus one inch of trace is about 2% of your clock period. How significant that might be will depend on how close your timing is to start with. But as long as your memory is placed fairly close to your DSP, you should have no problems. If your memory is placed far away, then you will have to take some care - it is generally more important to match signal path lengths, rather than to get the minimal length.

If you really are running at 150MHz - as opposed to pipe-lining stuff around a system on a 150Mz clock - you will certainly need to keep a close eye on propagation delays.

Having said that, I got a lot of my fast logic experience on a system using 5nsec ECL SRAM with an 800MHz master clock, originally intended to run with a 50MHz read-recompute-write cycle, which ended up with a

In that system, track lengths really didn't give us any trouble. Mis-routed tracks with lots of via's did, and a couple has to be replaced by sub-minature coax links.

Anything that will do signal integrity should do propagation delay as well. In general, track propagation delays are smaller than production variation on propagtion delay, but a meticulous designer will check both.