Why OR gates?

If you tie the outputs of two TTL gates together, and one output is a 1 and the other a 0, you end up with a short corcuit between VCC and ground through the gates. For a 74Fxxx, for instance, you will draw about 100 ma, and the resultant output will be neither a 1 or a 0.

Tam

OK. I knew it was something stupid. I was thinking that gate outputs are high-impedance, but it's the inputs that are hi-Z. Duh.

What I'm trying to do it select one of three inputs without using a lot of chips, or wasting a lot of gates. I know that there are MUX's, like the 74153 that have dual 2 to 4 selectors, but I hate to waste the second MUX. I was hoping to use three AND gates with 3 enable lines, but then if I need an OR gate, that's another chip...probably a quad.

Don

If you'd asked where this belongs, sci.electronics.basics I'd take a shot at answering it. But since you can't bother to find the right newsgroup, I won't.

This is not a design question, it doesn't belong in a newsgroup about design.

Michael

Well, sorta. TTL inputs are medium-high (Z loading on an output is a factor based on number of inputs driven). CMOS inputs are quite high (only distributed capacitance of multiple traces/inputs is a rise/fall time factor).

Fred

Oops, sorry Michael - meant to reply to author.

Well, sorta. TTL inputs are medium-high (Z loading on an output is a factor based on number of inputs driven). CMOS inputs are quite high (only distributed capacitance of multiple traces/inputs is a rise/fall time factor).

Fred

DTL is what you seem to want to do. You can add steering diodes.

greg

Of course you can. It's a very common construct called "Wired OR".

No problem with open-collector outputs. Otherwise just add some diodes.

Since you are using TTL, and since TTL usually has OC outputs (but do check the datasheets of your chips to make sure), there is no problem. With push-pull outputs (such as CMOS, like the 40xx or 74HCxx series) what you have in mind is not only bad design, but it simply won't work at all.

robert

diode-or :) just make sure they dot drop the voltage below TTL threshold (which is why they are not generally used for OR gates)

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This is badly phrased. There are TTL parts with open-collector outputs

- the SN7406 - for example, and these can be used to build wired-OR functions.

Most TTL parts have a totem-pole output which can both source current (1 or high state) or sink current ( 0 or low state) and you shouldn't use them for wired-ORs,

Emitter-coupled logic (ECL) uses an NPN transistor as the output driver, and can only source current - it relies on a pull-down resistor (usually 50R to -2V) to provide the pull-down current to generate a low (0) output, and all ECL parts can be used to produce wired-ORs, though it isn't a good idea if the gates being OR'd are more than an inch (a few centimetres) or so apart.

-- Bill Sloman, Nijmegen

I did not know that.

This won't work into TTL because it leaves the input to the next stage floating, which is a mostly ONE. If you add a pulldown of sufficiently low value you won't be able to drive it. This basic configuration will work if you use resistors, instead of diodes, and connect them to the base of a transistor. Connect another resistor from collector to ground. What you have now is a NOR gate; so, you need to invert that.

This will work. Notice, Rich said to invert the signals. You will need a ~10K resistor from the diode outputs to VCC.

Tam

You didn't know that because it is NOT true.

Tam

I would not think this reliable as the diode puts you at the threshold instead of in the low region.

Best, Dan.

Eek. You're right. I guess it worked for me before because I didn't know that, much like the bumblebee doesn't know it's impossible for him to fly. ;-)

(I probably just lucked out on margins & stuff.)

Thanks! Rich

OK, this is your design and I won't comment on it. But from my short (25 years plus) time spent in various designs I can assure you one thing. Mr. Murphy is a constant companion so designing to evade his inerference is futile (Star Trek). The problem is to ensure that your signals don't create low-high couples, and for this you have the OR gate as a bouncer. Not only that, but it is a component in Boolean logic, and we love to use math before assembly.

Have fun

Stanislaw Slack user from Ulladulla.

Well, I'm only marginally right. :)

Best, Dan.

Usually when I say that in a meeting people understand it to be dead- pan sarcasm.

However, I don't know how to inflect that in a newsgroup post.

...or OR and NOT.. How about a BUT gate, or a MAYBE gate?

---> BUT NOT AND MAYBE XOR ?