Braille

You are certainly free to solve each of the outputs, individually. Then look for common parts of each of those solutions so you can share them.

You might also use a 1 of 16 decoder, and use simple gating to code the Braille outputs from combinations of those decoded states. For example the UL output is a NOR gate connecting decoded states 0 and 9 states (Only outputs a low if one or both of its inputs is a high).

Or program a 4 bit wide, 4 input ROM.

John Popelish wrote in news:CoGdnYGiifMi_

That's the approach we took about a month ago in my digital design class. There's a lot of K-maps to draw... best use graph paper or a rubber stamp with a 4x4 grid. ;-)

Puckdropper

It depends if this is a homework question, or a real application.

If it's a homework question, they're probably looking for a reasonably optimized solution based on the stuff that has been taught already, such as Karnaugh maps. In that case, I would just follow the methods for each output individually. A quick glance at the table doesn't show any obvious optimizations you can get by combining partial terms.

If it's a real application, there's probably a microcontroller involved somewhere, in which case it would be easiest to do the conversion in software by a lookup table.

For a hardware implementation using the lowest parts count, I'd recommend a small PAL, or similar programmable logic device.

The sneaky part of this method is that a less than optimum solution for one of the outputs may be best because it contains the most reusable intermediate terms to be shared with other outputs. Either you make an exhaustive (and exhausting) list of all possibilities, or you hope for luck or insight in your quest.

The first step would be to define the optimum and the constraints. One could optimize for speed, area, part count, low fanout, ... and use all kinds of constraints: only 2 or 3 input gates, no XORs, only NORs, not more than N inverters, glitch free.... the list is endless. Without proper specification, you wouldn't even know where to start optimizing.

Of course, in the real world, these optimizations aren't of much value anyway. Discrete gates are typically only used in the simplest of applications where optimization is usually easy. For more complex designs (even including OP's), you would typically use a programmable logic device, and write down the desired outcome in a HDL, using a table, case statement, or a unoptimized boolean expression. The tools will do the boring work to make sure it meets the timing and area constraints.

Karnaugh maps are mostly an academic toy. They're useful as a means to provide insight into digital logic (as long as students understand why and how they work), but rarely provide an optimal solution in terms of real-life criteria.

If you factor in high latency, the binary group can be *read* at

Thank you guys

John, if you please can send me that drawing again please, i will appreciate it. thank you