I've recently designed a circuit in 74LS (that I plan to redo in 74HCT) that requires just a single OR gate. Rather than haul in an entire IC I was intending to replace this with Schottky diodes on each line.
I couldn't find a lot of information online about this being done, so I thought I would ask the good people here if there's any unwanted side-effects (beside the forward voltage drop) that I should be aware of.
requires just a single OR gate. Rather than haul in an entire IC I was intending to replace this with Schottky diodes on each line.
thought I would ask the good people here if there's any unwanted side-effects (beside the forward voltage drop) that I should be aware of.
Look up "DTL" and do it right. Don't be a hacker. ...Jim Thompson
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requires just a single OR gate. Rather than haul in an entire IC I was intending to replace this with Schottky diodes on each line.
Take a look at Fairchild's NC7SZ57 / NC7SZ58 chips. One of those may be smaller than one diode package (or at least not much larger) and with one or the other of them you can get pretty much any two-input logic gate. Really handy for one-offs and prototypes.
requires just a single OR gate. Rather than haul in an entire IC I was intending to replace this with Schottky diodes on each line.
thought I would ask the good people here if there's any unwanted side-effects (beside the forward voltage drop) that I should be aware of.
With 74LS circuits, your diode gate is a bad idea: The TTL logic is designed to sink current from the inputs into the outputs, and your gate is going to do just the opposite.
With CMOS, the situation is easier, but the gate will be sloow.
On the bright side, it does guarantee a proper LS TTL or CMOS level.
Instead of using diodes, you can use a Diodes Inc. 74AHCT1G32SE-7 SOT-23-5
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The diodes could work okay (assuming HCMOS), but there will be a time constant on turn-off related to the resistor value and input+stray capacitance, and, of course, there will be static power dissipation due to the resistor if either input is high, and you have to make the resistor high enough to guarantee enough noise immunity at the output taking into account both the diode drop and the output voltage under load.
requires just a single OR gate. Rather than haul in an entire IC I was intending to replace this with Schottky diodes on each line.
Don't. The low threshold for TTL is VERY close to the highest LS-series output-low specification. The best way to do an OR with LS TTL is with open-collector gates (in negative logic, two open collectors wired together with a pullup resistor, is an OR function).
If this was CMOS and high voltage (5V or more), the diodes would be a good option.
74LS00 needs 0.8V to reliably indicate LOW, and drives only to 0.4V (loaded). There's not any margin left if you add a diode drop.
You have to be careful with some of these. I used the 74LVC1G00 family in something and had horrible noise/crosstalk issues. After some fooling around, I discovered this family had about 2 A of shoot-through whenever the gates switched. The shoot-through lasted about 3 ns. It may be that parasitic inductance made the current look worse than it really was, but I was astounded by the magnitude of this current pulse.
I had to redesign the whole thing, taking the time to move from 5 V down to 3.3 V and switching to the
74AUP1G00 family. The power supply noise was not even measurable! (Looking at the datasheets, I chose this particular family because I assumed that the equivalent switching capacitance must be related to shoot-through and timing of the output drivers, and it was the lowest value I could find.)
Of course, nobody directly talks about shoot-through in their datasheets.
I've never tried to quantify noise from digital logic. I assume a direct decoupling cap of very low inductance didn't help? A 3 ns shoot-through short is just the sort of thing the power distribution system (PDS) is supposed to keep out of the other logic and analog.
Did you ever figure out exactly how it was getting into the rest of the board? Common resistance/inductance in the power/ground traces/planes maybe? A better topology for your PDS might have fixed this.
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