I can't find this in any jfet datasheet so how is it calculated? This is a common parameter for mosfets but why not jfets? Is it simply the some of Vdg and -Vgs?
- posted
13 years ago
Vds breakdown of jfet
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- posted
13 years ago
Odd. In the J310 data sheet from Fairchild, it's the very first parameter listed under "Absolute Maximum Ratings" (25 volts, in this case).
The same is true for the On Semiconductor 2n5457 - Vds maximum is the first thing listed and is also 25 volts.
NXP BF556A data sheet... Vds is the first thing listed under "Quick Reference Data", as +/- 30 volts.
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- posted
13 years ago
Very strange, all the datasheets I have do not have Vds but Vdg.
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(not all are fs and not all are rf)
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- posted
13 years ago
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Gives Vdg!
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- posted
13 years ago
Assume a common source.
If you adhere to the data sheet, Vdg(max) = 25V. So, you can have 25V on the drain if the gate is at zero V.
If you have -25V on the gate, the drain must be zero to comply with the specs. Also note that this is the max for Vgs.
If you have 10V on the drain, you should not have more than -15V on the gate.
It seems straightforward to me. If I've missed something, please point it out.
John
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- posted
13 years ago
Um, we are not talking about what Vdg is but the fact that a lot of datasheets give Vdg and not Vds.
Does Vds = Vdg or Vds = Vdg - Vgs(off) or what?
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To me, the maximum Vds would actually between in cutoff in which case it might be smaller than in saturation. The datasheet suggests they are the same or it only gives some absolute maximum over all gate voltages which is wrong if Vds = Vdg - Vgs(off). Of course maybe they derate them in such a way that it doesn't matter. e.g., technically Vds = Vdg - Vgs(off) but they actually set Vdg = Vds which is smaller than the true Vdg.
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- posted
13 years ago
Keep in mind that JFETs are usually symmetrical. What matters is the junction breakdown.
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- posted
13 years ago
Vgs(off) is a parameter, not a limit. It is the voltage required on the gate to produce a drain current of 200uA, in this case, with Vds=15V.
See table 5, "Limiting Values"
Vds max +/-30V Vgso -30 (open drain) Vgdo -30 max (open source) Ig max 10mA
Basically, you shouldn't exceed 30V between any two pins, nor (both constraints apply at once) are you allowed to forward bias the gate such that more than 10mA flows (nor can you exceed the maximum power dissipation or junction temperature)
On the 2N5457 data sheet, you should keep Vdg < 25V and Vgs > -25V, so if Vgs can be as low as -10V you should not exceed 15V Vds. Clear as mud?