The following is a simple JFET source follower amplifier:
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Every combination of the switches work as expected. When I mock up this circuit it does not work for direct coupling to any degree like the simulation. The main issue is when the low side of the AC source is connected to VDD. In this case I'd expect the DC bias point to be 5V. When it is instead grounded the DC bias point depends on the R2, R3, and R4.
What you really want is the source voltage to equal the gate voltage. This is hard to do with a Jfet because the IDSS is all over the map. Further, you are modulating this current with the swing of the fet since the voltage across the resistor R1 is varying with the source. This adds distortion to the buffer. Now if you are building one buffer and can tweak it, I'd substitute a current source pulling on the source of the fet. It would have to be variable to cover the range of IDSS. If you pull some current equal to the IDSS of the fet, then the VGS will be zero. You could connect directly to the gate of the jfet, assuming the signal driving the jfet isn't cap coupled.
I've never opened up a fet probe or have seen the circuitry, but I suspect they work as I described above. The fet probe has a bias that you adjust by hand to get zero offset.
What you really want is the source voltage to equal the gate voltage. This is hard to do with a Jfet because the IDSS is all over the map. Further, you are modulating this current with the swing of the fet since the voltage across the resistor R1 is varying with the source. This adds distortion to the buffer. Now if you are building one buffer and can tweak it, I'd substitute a current source pulling on the source of the fet. It would have to be variable to cover the range of IDSS. If you pull some current equal to the IDSS of the fet, then the VGS will be zero. You could connect directly to the gate of the jfet, assuming the signal driving the jfet isn't cap coupled.
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It doesn't have to be exactly but ideally from what I read a an ideal jfet has VGS = 0. I'm am seeing this behavior from what I remember but simply getting the gate voltage to be biased properly is the problem. It may not be an issue with the jfet at all but an issue with the source.
I assuming you mean that I have to pull off enough current to zero Vgs which will have to do with rs. rs is ~= 50 ohms for the jfet I have(if using a dmm is of any use measuring it) and my source resistor is on the order of 100k. So whatever variations won't matter much. I don't need perfect matching at this point.
I do not know if the source is CC'ed or not. I assume it is for the sound card but it will not always be.
Yes, though in reality you can never get a perfect match, so you use the fet with the smaller IDSS as the current source. Or use the part with the higher IDSS and the resistor. The idea is to not enhance the jfet used as a source follower.
In any event, the jfet as a current source is a good suggestion. Better temp tracking too.
In some bicmos processes, you can make jfets in the epi. They are not terribly useful, but they do come in handy in start up circuits since you can depend on the jfet with vgs=3D0 to be the first element drawing current. In most applications they would be smaller than the second best choice, i.e. a resistor.
The sound card could be AC coupled if the device runs on a single supply. If it uses an DC/DC inverter, it could be direct coupled. In any event, you can never be sure since this buffer would be used with different sound cards, so put a high value resistor to ground to insure a place to sink the gate leakage current.
A resistor pulling on the source is a bad idea. It will modulate the current in the jfet and cause distortion. Yes, I am repeating myself. Further. if the input is line level, say you have 800mv into 50 ohms. That is 16ma, which exceeds the IDSS of the jfet, so you have enhanced it.
BF862s have high enough transconductance to use them either way up, at least if they come from the same wafer--the transconductance is around
30 mS, so the typical I_DSS spread isn't big enough to cause a lot of gate current to flow if the top one gets enhanced a bit. (For a product you'd add a source resistor to the bottom one, but it wouldn't have to be very big.)
When you don't care too much about the offset voltage, e.g. in a current-feedback TIA design, you can save some parts that way. JFET followers running into low noise bipolar op amps are the bee's knees for a lot of low-noise jobs.
The OP was using 2N3370. The BF862 is really impressive. If you go through the LTC app notes, they toss the part in a lot of circuits. Kind of power hungry, but you know the expression about having to break a few eggs.
So you use the BF862 to get low bias current, then hit the BJT for gain? Off the top of my head, that sums the noise of the two devices in RMS fashion, i.e. without gain with the fet, the BJT sees alll the jfet noise.
Sure, but when running a BF862 single ended into an ADA4898 bipolar op amp, the total is something like sqrt(0.8**2+0.9**2) = 1.2 nV/sqrt(Hz), and if you bootstrap the JFET, you can get < 1 pF of input capacitance and tens-of-picoamp input currents. That combo is good for a lot of ills, especially with a capacitive- or current-feedback design.
If you over-bootstrap the fet drain, I suppose you can get to zero gate capacitance, and even take out a bit of PCB parasitics. I suppose there will be a small noise penalty, since whatever amp drives the bootstrap will add a little noise of its own.
That works fine if you don't overdo it. I've also used a little bit of negative capacitance from the op amp output to the FET input. Since the BF862/ADA4898 combo wants to be noninverting anyway, it's easy to do--a small cap from output to input.
Any of those sorts of tricks that use only signal-path nodes can't improve the SNR, they only change the frequency response. Stuff hung off the side (e.g. bootstrapping a cascode, or bootstrapping the bootstrap) can improve the SNR as well as the frequency response. (Not exactly a free lunch, maybe a 25% off coupon.)
Over-bootstrapping is an off-to-the-side trick, so it probably has lower noise than ordinary negative capacitors, but it does add circuit complexity right at the high-Z stage, where you really want simple behaviour.
One thing I've never tried is a small negative conductance in the source load, e.g. -300 ohms (vs +30 for the small signal source resistance). That would make the follower's gain slightly greater than 1, so the C_GS contribution would go negative. Since C_GS is much bigger than C_DG, it might be easier to tweak while maintaining stability. I don't know if the nonlinearity of C_GS would be a problem there.
Normally it's part of an integrating servo, in which case I don't care much about the offset, or else there's another op amp off to the side snooping the summing junction and adjusting the current sink on the source to exactly I_DSS. That raises the noise at low frequency a bit, but the 1/f corner of the JFET is around 100 Hz anyway, so usually you don't really notice it.
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