looking for accurate n-jfet spice models

The problem isn't so much getting a spice model that matches one particular JFET, as it is dealing with the wide variations in JFET Vgs at a given drain current, typically 1.5V or more for parts within a given production run and much higher otherwise. This is the primary difficult issue you have to solve in your design, and in your spice modeling as well.

That said, it's true spice JFET models do fail to properly model the subthreshold region. The JFET drain current should follow an exponential law, exactly like BJTs, where Id = k1 e^(Vgs/nVT). I have observed n = 1.05 across many parts. Instead the JFET drain current rapidly plummets to zero, which means the models report an artificially high transconductance at low currents.

This problem is similar to the one we encounter in the subthreshold region in MOSFET spice models, but in practice it's not quite as painful for JFET users. That's because those of us that use power MOSEFTs are often using them in the subthreshold region or in the transition to subthreshold, where the model errors are devastating. The solution, should you need to model JFETs at *very* low drain currents, is to modify the model as I described for MOSFETs.

By contrast, most linear-amplifier JFET design use occurs in the Id = k (Vgs - Vth)^2 region where the spice JFET modeling is pretty accurate. Here I've found the parameter k can vary from manufacturer to manufacturer for a given type, such as the 2n5458 from ON Semi or Fairchild, but stays the same for a given manufacturer, even over different runs. But as I said, the variation in Vth is dramatic. Again, this is for the "saturation" region, with Vds > 1V, etc., where the JFET acts as a transconductance device, with its current programmed by Vgs-Vth, and is only a weak function of Vds.

As for the other popular JFET "linear" region, at low Vds voltages, where the JFET acts as a resistor programmed by the gate voltage, namely 1/Rds = 2k [(Vgs-Vth) - Vds/2], I haven't investigated to see how well the spice models do. But again, large variations in Vth for real JFETs will get you into trouble if you're not careful.

Sorry Jim, but this model has the same old complete failure to model the subthreshold region. Below 1uA it drops like a rock, and it's erroneous above that... Of course, as I said in the other post, given the low currents at which it happens, this modeling failure isn't so devastating as it is when using power MOSFETs in their linear region.

Yep, There aren't many users concerned with JFET behavior below cut-off.

...Jim Thompson

Hello:

I am designing an AGC loop using a low power n-jfet. I would like to check it on Spice beforehand, but I have the impression that the models available are often not quite trustworthy.

So, I am looking for accurate models of the behaviour down to the cut-off voltage, for low (+ and - 0.5V) Vds, for the parts like 2N4339, J201, J113: Vgs(off) between -0.5 and -3V, Rds(on) less than 1.5k at Vds=Vgs=0.

Thank you for any help.

-- Andy

Are you operating in the starved region below cut-off?

Or are your problems with linearity issues in the AGC? There are biasing techniques to linearize the resistive behavior of JFET's

I haven't seen your "other post".

...Jim Thompson

You probably need a zero in your control loop.

...Jim Thompson

Let me chime in and say that Win is absolutely right about the JFET variation. I have a design where I designed JFETs in for volume control of two channels and AGC (AVC) for two audio power amp channels. I gave up on the AGC due to the variation between JFETS. On the volume controls, I added trimpots to set the max Vgs and still about 1 out of 8 JFETS are too far off for the circuit and production replaces them. It's almost Select At Test which is an expensive no-no in production. I won't make the mistake again of trying to use JFETs in this manner.

Carey

Thank you. Actually, this model was in my list, and I have managed to track down the strange behaviour of the circuit to some problem with the way the simulator was handling the inductances! But the sub-threshold inadequacy of the models pointed out by Win Hill might indeed be a source of inadequacy of the simulated behavious of my circuit. Please see my other post.

-- Andy

Yes, I realise this is a challenge. At this time I believe I will be able to cope with these variations.

Indeed, this subtheshold inadequacy might be a key problem in my simulation. I am trying to use as much dynamic range of the Rds as possible, which, for some situations, brings the control loop stability point close to Vgs(off). But the overall dynamics is such that the control voltage easily overshoots below that Vgs(off) in those case, and as you say the Ids drops like a rock - and the control loop does not converge. I am not sure whether the correct exponential behaviour would cure this, but I am very interested.

By the way, getting Ids drawed against Vgs, I can see the Ids _decreasing_ on the left of Vgs(off) as Vgs increases, n-jfets!

Was this modification explained in this NG / a.b.s.e.? Is it in the discussions about 2n7000?

Thanks!

-- Andy

The control loop's drive of the n-jfet's gate sometimes overshoots below cut-off, and the loop does not converge. I am not sure the correct exponential model would provide for convergence, but I would like to try.

A resistance between the drain and the gate, with an equal resistance between the gate and the drive? I have included this, the linearity in the signal path looks ok.

I have posted it after the above reply, in reply to a post by Win Hill. I hope you can see it now, I thought I would not duplicate the content across different posts. I am sorry if this caused you an inconvenience.

-- Andy

Note that a few simulaters, including SuperSpice, support the Parker-Skellern jfet level=2 model

There is pdf on that page that describes the model, including subthreshold region.

Kevin Aylward snipped-for-privacy@anasoft.co.uk