Triggering Mosfet with Vgs (2*Vds) > Vds????

Not sure what you mean by "any inconvenient," but I can tell you it's not an uncommon situation, and involves no unusual difficulties if a supply voltage higher than Vds is available to power the gate driver.

I meant that I could not find any written material supporting that way of using the Mosfets. Anyways, if that approach is usual there should not be any inconvenient. ;)

Do you have any example when to use that configuration?

Greetings...

Franco.

It might be very inconvenient if Vds was 600VDC.

Best regards, Spehro Pefhany

You'd want a device without protection diodes on the gate. The SD214 comes to mind.

http://www.ortodoxism.ro/datasheets/linearsystems/SD214.pdf

I've no idea where you could buy one these days - Farnell doesn't seem to stock them any more. Joerg will know.

-- Bill Sloman, Nijmegen

Thanks, I needed that!

If you study your written materials, app notes, etc., you'll see the issues of Vgs to turn on the MOSFET, and Vds are independent; there's no relationship between the two. The most common situation where Vds is much lower than Vgs occurs when a MOSFET is switched on and Vds is nearly zero. And of course we expect to use a reasonably-high Vgs voltage, such as 12V, etc., to insure that the MOSFET is very well ON in that case. Later, when Vgs = 0 and the MOSFET is OFF, the drain voltage is free to rise, e.g. up to the Vd supply voltage, etc, but consider, why should this be very high at all? For example, the MOSFET might be acting as a rectifier in a high-current, low-voltage SMPS, delivering 1.8 volts at 60A to a microprocessor. High Vgs voltages are sill required to turn on the MOSFETs.

Student, wrapped up in equations rather than thinking things through.

...Jim Thompson

"America: Land of the Free, Because of the Brave"...

Patriotic American, wrapped up in fights rather than thinking things through.

It confuses me that there are some curves indicating that Vds > Vgs - Vth. But, as you mention, the channels (N or P) should be created independent of the voltage between the terminals.

The mosfets have are commanded by a higher Vgs because I am using a Brushless Driver motor chip that internally regulates up the voltages in the gates for driving the upper mosfets in three half mosfet bridges.

On the other hand, the voltage being sent to the motor may drop under the level of that Vgs generated by a bootstrap cap.

Thanks for the answer!

Franco.

You must be new around here. Jim's been our resident brownshirt for a number of years now.

Cheers! Rich

Now that's no way of making friends.

An exhibition of one of the many reasons I kill-filter on "@gmail.com" ... sort of a free first-cut IQ meter ;-)

...Jim Thompson

-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |

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The US population are pretty easily manipulated by corporate lies, but eventually they sort themselves out.

Win once spake:

"Americans generally do the right thing, after first exhausting all the available alternatives"

It's a pity the US don't look to the French for methods of telling the Gubberment that they suck

But the RIAA/Exxon brigade will not permit stuff like this to happen in the US

Martin

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Martin

To illustrate Win's point with a real-life example: Take a single fuel cell. It generates about 650mV and an incredible current may be available. However, you cannot really use 650mV directly for anything electronic. So, a few big FETs are arranged, typically in two banks. One bank pulls down one primary, then turns off and now the other pulls the

Those FETs still need 10V or so of Vgs to switch reliably. Mostly those kind of converters generate higher voltages at their outputs but that won't be there without first switching the FETs a few times. Therefore, a little helper oscillator is used that generates 10V or more at low power. This voltage is used to drive an oscillator, the regulator loop and so on. The oscillator feeds buffers and those drive the FET gates hard from 0V to 10V and back.

So here you have it: Vds is between 0V and 0.65V all the time while Vgs is between 0V and 10V.

Those are all covered by news:sci.electronics.whining eurosheep.