Unified FPGA Development Suite

Wrong. Procedures are not concurrent in C. C is a sequential language.

Spoken like a programmer.

IOW, it's a bastardized hammer to drive screws.

SystemC C

SystemC C. It may walk like a duck, but it's a DoDo.

No, you're the one trying to screw around with C.

Useless things. I don't know about you, but I have yet to design in a touch screen. I'd like to but the boss doesn't pay me to screw around with hammers.

Ok, then is no different than any other *free* development system from the chip manufacturers. Slaughter was suggesting that it was the FPGA fabric development tool.

Proprietary is enough to kill the deal. That's a major advantage of HDLs; all you need is a text editor and you're good to go. Indeed that's the one reason I won't use schematic entry for the data flow. Data flow is extremely tedious in HDL but locking it into a tool defeats a major purpose of HDLs.

SystemC, perhaps. If the love is so great for C why not Verilog. It's almost as ugly as C.

I misunderstood earlier. I was looking to switch schematic capture tools a few weeks ago but we're pretty much locked into Allegro. I'm pretty much stuck with Crapture. No point in going there, then.

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If your software can output a *.JAM file, you can make your own JTAG cable for way under $150.

Altera published the code for a JAM/STAPL player some years back. I have a hacked version that I use all the time. The very nice thing about it is that it can be made simple enough that you can write the instructions for using it on a single page.

On Oct 11, 8:32=A0am, krw wrote: [...]

Even things like having to work around bugs in the various compilers makes for troubles in porting between tools. The Altera VHDL tool doesn't do the right thing when you assign Z to a signal. You have to use their tri() kludge.

It is too long ago now so I'd have to paw through the source code but there was another thing that the Altera tools messed up on that was more major.

Cypress used to make CPLDs but unfortunately, I designed one of them in so they decided to get out the business. Their development kit was fairly nice. It wasn't as huge as some others and seemed to be targeted at just doing what was needed to make VHDL get into an IC. It didn't have a lot of mysterious features to mess you up. [....]

If I didn't have to interface with others, I would use the GEDA tools. They keep all the files in ASCII. This means that you can make your own tools to do funny things you may decide are needed like finding all the package types in the design etc.

$399

boards:

The STAPL player is used for all their CPLDs as the means of in-system programming. They have the source on their site. All you have to do is add the low-level I/O routines for your hardware (e.g. PC printer port) and link it all together. It's so easy Actel swiped it. ;-)

Haven't quite gotten that far with Altera yet, but is this in internal 'Z' or inferring a 'Z' in an IOB?

Tool bugs are certainly a problem, enough that I'd dump a manufacturer if they were too buggy. Times have changed, though.

Things have gotten a *lot* better over the years. A decade ago I bought the Synplicity tools because Xilinx' were so messed up. I wouldn't today.

That's even easy with OrCAD Crapture. There are a lot of things like that are easy in Crapture. Unfortunately, other far more important things are impossible. :-(

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My hacked version(s) will compile on a 16 bit MS-DOS machine with BC and work even for the large CPLDs and if compiled by gcc, it works on Linux. It flips the different code in and out with #ifdef statements.

The assignment of the 'Z' was some layers deep and the signal came out to a pin at the main level.

At least, they need to publish a list of them and the work-arounds for them.

I tried Crapture and after it munged the whole design, dropped it. I use the clunky old DOS Orcad. It does all the things needed.

Except that it's easier to use and "unified" (all in the one package) as the original thread title says. Altium have been flogging the "unified" title for years now.

Well that's just wrong, obviously.

For you, others may not care so much.

Sure, but tell that to a beginner trying to crack into the world of FPGA's...

The advantage of a C-Hardware compiler is that you can write and refine your app in the soft processor in C (easier and more familar to most than a HDL, and maybe quicker recompile etc because you ain't rebuilding the FPGA) and then once your app is finished you can decide where you want more speed. Need a certain C function to execute quicker?, no problem, just drop it into the C-Hardware compiler and it automatically converts your that C code's function into HDL for you. And another advntage is you can continue to develop it in either C or HDL, your choice. It means that those familiar with C, processors, and sequential language programming can potentially take advantage of FPGA's without learning a HDL. Once again, not a solution for everyone, but very useful for many.

Altium's schematic-only (+FPGA/embedded) solution is either $999 outright or $49/month if your accountants prefer the 12month lease thing.

Dave.

Yes, that's a common problem. Xilinx has the same issue. The IOBs have to ge at the top level of hierarchy. :-( Actually, I find that to be good practice, but a PITA.

For things like that there usually are, though not tabulated I guess.

I'd try the DOS version if I could. Crapture 15.7 crashes often (10-20 times a day, if I'm really using it) but usually saves on a crash. A couple of weeks ago it crashed taking all open files with it. Fortunately I'd just made a copy of all of the work. I "only" had to figure out what I'd done in the last couple of hours. It was only a day wasted. I wasted a lot more than that before figuring out that their hierarchy tools didn't work.

If you say so. I find all of the packages pretty easy to use now. I picked up the Altera stuff in a few hours (after using Xilinx). Actel wasn't any harder. I haven't settled on a device yet (other than not Xilinx), so have been trying all of the free tools.

I understand. I worked for an all Xilinx shop and interviewed with a couple all Altera. Proprietary didn't matter to them either. In the job I'm in now, money matters. I don't work for the government anymore. ;-)

No doubt, FPGA design has quite a steep learning curve. I learned FPGA design and VHDL on my own. While I'd done a lot of design, none of it was in an HDL. At least I didn't come from a C background. ;-)

You sound like you're in marketeering.

I've seen people who believe this. I've also seen the crap they turn out.

I thought it was $399 (per this thread). OTOH, right now they prefer $0. I prefer that they continue to make payroll. ;-/

You may be able to lay your hands on a copy. They sold quite a few so there should be a lot of honest copies out there not in use.

I run it under dosemu in a linux box.

It is Windoz software. The default action is to crash without warning. You need to go into the "hidden settings" dialog and set the crash to "daily" instead of "random". This way at least you would know that it will crash just once a day.

What ever you do don't set your network up as a "windows domain" network and save the schematics in any folder that windows created. Make your own folder with your own name. For reasons that aren't clear, a network error will cause it to mung the files if you don't do this.

Never bring up "outlook" when Crapture is running. They interact in a funny way that tanks Crapture.

I use the DOS one. The "place sheet" works fine but there is one thing that you must never do. Never make two sheets in upper level use the same file to do repeated circuits. The net list generation doesn't work as documented in that case.

My hacked version(s) will compile on a 16 bit MS-DOS machine with BC and work even for the large CPLDs and if compiled by gcc, it works on Linux. It flips the different code in and out with #ifdef statements.

--- I downloaded that and DirectC from actel. The DirectC is C source that I believe you can use on just about any uC that you can compile it with. Should be easy to look at the code and figure out how it bit bangs the data(and interprets it). Although that could be a lot of work...

Somthing is wrong with your math: $49/month *12 = $588.

Likely all in the landfill.

Not that it matters, but I can't do Linux.

Daily would sure be a step up! The funny thing is that it usually tells you that it's going to crash. "I'mmm crrraassshhhhiinnnnggg, do you want to save?".

Not sure I understand you. "Save as" doesn't seem to cause problems. Simply selecting a block of components and moving them is the most likely cause of a crash.

Hmm. Outhouse is always running.

It's not only the netlist. Nothing works, though it tries to fool you into thinking it did. Without "complex" hierarchies, hierarchies are rather useless.

Didn't say how many months. Ever bought a used car? ;-)

I didn't do any math:

The two prices are not equivalent. The 12 month one times out and become useless after 12 months unless you keep paying more $$$. The $995 price is one-off for a perpetual license (i.e. never expires, use it forever) that's why you pay more for it.

Dave.

'If your accountants prefer the 12month lease thing' sure implies 12 months.

Yes, but I always paid cash. The only monthly bills I've ever had was the utilities & house payment.

or

...and at the end of 12 months you have?

That's just un-American! (That's all I have now, though we do buy things with the "no payment for 12 months" thing.)