The Way to make 61.44MHz clock from 10MHz and 1PPS!

And every bit as usefully.

....... Phil

I think what you mean is that you want the two frequencies to be coherent.

Tam

Your requirements aren't very clear. Is the 1 Hz derived from the 10 MHz? How does the 1 Hz sync help you?

Cheers,

Phil Hobbs

"THE" way??? "A" way is a PLL. Find the largest frequency which multiplies by integers to 10MHz and 61.44MHz, since you already have the 10MHz to work with. Set those integers into the reference and VCO divisors of a programmable PLL. You may even be able to find one with an integrated silicon VCO that will do the job for you, but if you want low phase noise/low jitter, plan on using a VCXO in the loop.

Quiz: what's the frequency, and what are the integers? Why use the highest such frequency?

If you don't always have the 10MHz available, use a VCXO that's stable enough to hold your desired tolerance for the time the 10MHz is unavailable.

Or would you rather lock to the 1PPS? (Why, if 10MHz is available??)

Cheers, Tom

Quiz: what is the frequency and what are the integers?

And more useful by far than Philthy Phil.

This would work. As Tom Bruhns says, you'd want to use a VCXO as your

A DDS chip doesn't have any problem with non-integral frequency ratios. Check out the Analog Devices AD9859 and comparable parts

This has a built in phase-locked loop controlled reference oscillator, which you could run at 200MHz locked to your 10MHz reference oscillator, and use to generate a 61.44MHz output. It would only be producing three samples per cycle of the 61.44MHz output (3.255308 ...) so you'd need a good anti-aliasing filter on the output.

If you look further down their product list you may be able to find something that can lock a faster clock to your 10MHz reference, which would give you more samples per cycle at 61.44 MHz and let you get away with a less elaborate anti-aliasing filter.

-- Bill Sloman, Nijmegen

If you have too very stable frequencies, you can remove one divider chain. A simple flip-flop clocked from the output of a divider on one signal and sampling the other will work as a phase detector. You end up with some "phase ripple". Think of it like this: ASCII art.

"Late case"

--- --- --- --- ---

--- --- --- --- --- --- Undivided

--------------- Divided

---------------

???????????HHHHHHHHH Flip-flop output

"Early case"

--- --- --- --- ---

--- --- --- --- --- --- Undivided

----------------- Divided

-------------

?????????LLLLLLLLLLLLL Flip-flop output

In this case I'd leave out the 768 divide to save the most flip-flops, if the timing will allow.

Yeah, that should usually work, provided the VCO pulling range is less than

Tam

See 4/25/2007 9:56 AM

Some reasons to consider doing it with a 22CV10 :

Div 125 may fit into 8 or 9 sections of a 22V10 and the phase detector into what is left of it.

If you use the "zero power" CMOS version of the 22V10, the current draw will be low.

The swing on the flip-flop is nearly 0-5V

Using a part that is not shared with anything else prevents a route for noise getting to the VCO.

Using one easy to get part to doa job will often score you attaboys.

On Apr 26, 11:06 am, "Tam/WB2TT" wrote: ...

Yeah, your posting hadn't shown up in my reader by the time I posted. Great minds and all that, I suppose, huh?

Cheers, Tom

Yes, a DDS will give you very good phase noise performance--but at the expense of spurs. An advantage of the DDS is that you don't need another good oscillator (the 61.44MHz one). A disadvantage is that if the 10MHz is not continuous (as might be implied by the base note), it won't do you much good.

As yet another alternative, from the analog camp (and a bit tongue-in- cheek ;-), if the 10MHz is continuous: multiply 10MHz by 768 and divide by 125; then filter. You'd do it in steps: multiply by 4 a couple times to get to 160; divide by 5 to get to 32; multiply by 4 to get to 128; divide by 5 to get to 25.6; multiply by 4 to get to 102.4; divide by 5 to get to 20.48; multiply by 3 to get to 61.44.

But the OP also indicated that the 61.44 should be somehow "aligned" with the 1pps. If he really means an edge of the 61.44 must be aligned with an edge of the 1pps, and if the edges of the 10MHz are not already aligned with the 1pps, he'll need to factor that 1pps in there somewhere. Does he really have a 1pps whose edge is jitter-free to within a fraction of a cycle of 61.44MHz?? Or is it a GPS output that could have tens of nanoseconds error in each pulse? As is often the case, the basenote was somewhat ambiguous about the real requirements and what is available to work from.

Cheers, Tom