Synchronous logic: Tpd<Th on the flip-flops of VHC family

That "1ns" column for a "minimum" Tpd over temperature is a bogus number. Any operating condition that reduces the Tpd will also reduce the minimum Th. The inportant thing is that Tpd will remain ~5x Th. You will encounter no problems.

But the 2ns is the minimum Th as well, so the operating condition reducing Tpd => 1ns will reduce Th => 2ns limit. This makes the safe operation (Tpd ~5xTh) impossible.

Additional thing which needs clarification is the upper limit of Th. Why do they specify the lowest threshold if the parameter is longer in reality? Do they want me to retain the input signal constant during the minimal time or it must last some longer? IMO, it is the maximal Th, which have to be satisfied (and specified) in order for the device to switch propertly.

Thanks.

That 2ns in the datasheet is the single value of Th guaranteed to work over -40

You should translate "minimum" to mean: can be removed no sooner than Th after SCLK transition. SER must remain valid for Th nsecs after the SCLK edge. Any additional time you hold SER is wasted, the clocking action is finished, and the SER input no longer has any effect. A maximal Th would be something like Tclk-Tsetup and has nothing to do with hold time.