1. Home
  2. Electronics Design
  3. Logic family compatibility

Logic family compatibility

When a 5-volt family drives a lower-voltage CMOS part, you run the risk of forward-biasing esd diodes and poking current into the Vcc rail of the victim chip. This is especially bad for 5V CMOS driving

3.3 or lower CMOS, as the curents can get high. Lots of lvcmos parts, including FPGAs, are *not* 5v tolerant!

TTL doesn't pull up as hard as 5v CMOS, but enough to poke some current anyhow; the schottky families are worse than classic old TTL. And some TinyLogic cmos parts and older FPGAs can be pulled up to +5 or so without drawing input current.

My test guys came to me last week with a bunch of boards that had the

3.3 volt FPGA supply running 3.7 or something. I was driving the Xilinx FPGAs from a 5-volt CPU, with 100 ohm current-limit resistors, and it still pulled the supply up. I scaled down the sense resistors on the 3.3 volt reg to dump more current, and that fixed it.

Right now, we're doing a board where we'll run the 3.3 volt rail at an actual 3.5 to guarantee we can legally drive some 5v cmos stuff.

All these different supplies are a real pain. They should have stopped at 5.0. The Spartan3 chips need 3.3 (or 3.5!), 2.5, and 1.2.

John

Reply to
John Larkin
Loading thread data ...

It's all driven by scaling... smaller geometries are faster (and take up less chip area per function), but can't tolerate higher voltages.

My general rule-of-thumb for nominal voltage is 10X the dimension in microns, thus a 0.18um process runs on 1.8V.

It's about to come to a halt though... those short-channel devices leak like sieves.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

Gosh, I don't know; maybe Jim does.

Some of the TinyLogic cmos parts can tolerate 7 volts or something with any or no Vcc, so there's likely no clamp path to Vcc at all... maybe a zener?

John

Reply to
John Larkin

I spent a few days doing homework on what logic family and voltage was compatible with what. This was a lot of work because each vendor has their own spin on the specifications (which makes me wonder why standards even exist, but that is another story).

Below is my take on things, and I would appreciate your comments if I have it wrong, or something is incomplete.

I refer to CMOS, NMOS, etc. as xMOS.

From To

---- ----------------------------------------------- TTL: TTL; LVTTL*; 3.3V xMOS*, LCX*, LVC*; LVT*, LVX*

LVTTL: TTL**; LVTTL; 3.3V xMOS, LCX, LVC; LVT, LVX

xMOS, 5V: xMOS 5V; 3.3V xMOS*, LCX*, LVC*; LVT*, LVX*

xMOS, 3.3V: TTL; LVTTL; 3.3V xMOS, LCX, LVC; LVT, LVX

'L's, 3.3V: TTL**; LVTTL**; 3.3V xMOS, LCX, LVC; LVT, LVX

*5 volt tolerance required, which they all seem to have today.

**Make sure that the Ioh is high enough to drive the loads.

Driving 5 volt xMOS is difficult because the Vih is .7Vcc, or about 3.5 volts. Thus, a 3.3 volt part can't do this without a device like a 74LVC4245 or 74LVX4245.

Reply to
Dave Boland

How does the ESD protection network work in (legitimately) 5V-tolerant logic? Do they just add a few more diodes in series with the diode to Vdd, or is it more complicated than that?

Jonathan

Reply to
Jonathan Westhues

It's usually more complicated. There may be stacks of diodes as a reference, but there is often some fold-back or latching built in as well as a filter to discriminate an ESD event from normal power sequencing. ESD tollerence is an art and there are a kabillion ways to do it (I know an individual with a hundred patents on such things).

--
  Keith
Reply to
keith

In article , Jonathan Westhues wrote: [...]

Some parts use a special MOSFET to ground. The MOSFET has a very high Vgs(th) and a low gm.

The real bummer is on things that can drive busses. The pull up transistor of the output section provides a direct path for an above the rails signal to get into the substrate and cause troubles.

--
--
kensmith@rahul.net   forging knowledge
Reply to
Ken Smith

Sn74ALVC164245 is a nice part. 16 bits of level shift, cheap, multi-sourced.

John

Reply to
John Larkin

Yes. However it's all proprietary. But the basics are that P-channel devices are built into N-wells. With proper design you can get the P-channel device to turn off and the N-well to float up.

This is also the way parts attached to a bus can be unpowered and yet not load the bus.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

IDT Quick-Switches are quite useful, as well.

formatting link 

--
  Keith
Reply to
Keith Williams

I agree that all the different voltages is a pain in the butt. However, what I really need to know is did I get it right?

I'll be connecting a 3.3V xMOS processor's I/O pins to the outside world and I want to protect it from voltage mismatches, so I plan to buffer the processor with a 3.3V 'L' part that will drive 3.3V xMOS, TTL, and can be driven to 5V when used as an input.

uP Buffers (LVC??)

---+ +---+ |----->| |----> 3.3V xMOS, LVTTL, 5V TTL | +---+ | +---+ |

Reply to
Dave Boland

John (and others),

I agree, but that part is needed mostly if driving 5V xMOS due to its high Vih, which is .7Vcc, or 3.5 volts.

What I really need is for a lot of experienced people to look at my chart (above, along with text) and tell me if I got it right. Once I feel confident that I understand the compatibility, it should be a simple matter to design the logic.

I practice, the logic will likely be an 08A quad AND gate so the processor I/O can enable/disable input and outputs. This is not the same as tri-stating, just useful in some limited situations.

Thanks, Dave

Reply to
Dave Boland

(snip)

I'm working on a DSL MODEM design now using a Mindspeed g.shdsl chip set and a Spartan 3 FPGA. The parts need 1.2V, 1.8V, 2.5V, 3.3V and

12V. The power source is 5V. Half the real estate is power and supervisory stuff. This was a major PITA because we only had 8 square inches (total) to work with.

Another FPGA gotcha is cases like the SpartanXL where the outputs are

5V tolerant. Prior to configuration done the IO pins have weak pullups to 3.3V. If you are interfacing to a circuit with resistance to 5V, then these IO pins will actually sink current to 3.3V until the FPGA is configured.

================================

Greg Neff VP Engineering

*Microsym* Computers Inc. snipped-for-privacy@guesswhichwordgoeshere.com
Reply to
Greg Neff

On the board we're doing now, certain overly-cautious engineers (you know who you are) noted that 3.3 wasn't a legal high for some of the cmos parts, so I just made the executive decision to run the Xilinx stuff at 3.5. This board has 16 isolated DAC channels, each under two square inches.

John

Reply to
John Larkin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.