Synchronizing T-flops?

Jeez, take a chill pill. More like, he needed to bounce a few ideas around, and USENET is a free and easy way to do that. I guess you have NEVER used any info you have found here, you just hang out to make fun of the vast unwashed...... Oh, I guess I missed the "Professional Circuit Designer ", never mind.

Jim

Another variation: use just 1 T-flop flopping on the negative edge of the input clock, and feed its output to the D-flop latching on the positive edge of the input clock. That way the D-flop's output will always lag 90 degrees the T-flop's one. This would save a flop, but might have the inconvenience of non-equal propagation delays of the T- and D-flops.

-- Andy

snip

yep, keeping the two paths the same is probably a good idea, that's the nice part about doing it by sampling I with Q to get the lead/lag, instead of changing the I/Q generation scheme which it sounds like has been verified in silicon

-Lasse

Plus the elementary nature of the question makes it more appropriate for s.e.b...

Yeah, everybody but Fred should go to s.e.b. He's the only one smart enough to post here.

John

WAAAAHHHHHHHH, SNIFF,SNIFF....... Boy, you sure showed me. Well, I'm over it. How about you?

Jim

If you have access to the guts of the T-flop cells, you can initialize them to your desired phasing just by injecting the right currents on the bases at power-up initialization.

In MSI TTL I used to see a similar trick done, but since the guts of the cells were not available it used a significantly ruder method of pulling the outputs to the desired "zero" states at power up through some NPN transistors. Different manufacturer's chips responded differently to this "initialization", of course some let their smoke out :-).

Tim.

I have access to all the guts... I designed them ;-) My problem is typical... customer has extreme power constraints, and I, personally, am leery of one-time reset-on-application-of-power situations, particularly in a noisy consumer-product environment. My preference is to use self-resetting circuits that "know" that they're out-of-kilter and get themselves back into rhythm automatically. Thus my latching (pardon the pun) onto the John/Chris D-flop "sampler" that tells me where I am phase-wise.

...Jim Thompson

John Larkin wrote in news: snipped-for-privacy@4ax.com:

Credit where it's due: it's John's D-flop as my post was in response to his (though I didn't actually quote what he had written) - I just spelt out the details; anyway, it's a well-known technique - at least to digital guys :-). Regards to you both. Chris

I doubt that a powerup reset would organize your phase relationships here.

We had a similar problem a few years ago, on the NIF timing thing. We had a 77 MHz biphase data stream and a 155.52 MHz (OC-3 rate) recovered clock. Since data recovery was ambiguous (depended on clk/2) we built in an OOPS counter that eventually decided we were at the wrong phase and XORd the recovery clock.

John

See...

Newsgroups: alt.binaries.schematics.electronic Subject: Problem Solution for S.E.C Posting - SidebandFix.pdf Message-ID:

Two D-flops, "WHOSFIRST", plus logic, "FLIPPER", convert commanded "SIDEBAND" to "SBINT", providing correct sideband selection irrespective of incoming phasing of quadrature signals 1056MHZ and

Thanks John and Chris!

...Jim Thompson