Super fast sample & hold under $10?

The min clock pulse width kind of gives it away. I don't think the sampler could possible be fast enough with that. It'll integrate over many nsec and that totally spoils the soup here.

That could be a problem unless there is a true flash ADC inside.

This one I really can't talk about but essentially I need to be able to digitize a very high frequency event in an equivalent time fashion, like on old DSOs. Or very fast new ones. A very fast ADC is far from ideal here but could work if nothing else is there. And it seems there ain't.

Yes, but diodes still have almost a pF when operated as quads, even the fancy Skyworks ones. Too much leakage when off. The only way to make that work would be a slew of T-configuration sections. Gets big and expensive. In an IC that would be easy to do but there seems to be not enough market. There are some boutique chips but those cost hundreds of Dollars.

Noise almost doesn't matter at all in this case. But the package of the SKY65050 somehow tells me that it's not a low capacitance device.

That's better than 0.5pF. I might take you up on that if I can't find a better solution. And they have SPICE parameters published which is really nice.

Some sort of gated active stage would work, maybe. Because reading the S&H cap may take some time.

Maybe I misunderstand this, but there is no threshold. The signal is not known and must be sampled to find out what the amplitude is at each time slot. That can change significantly within a few hundred psec.

Implementation with sloooooooow comparator and emulation of reset of capacitor (open/closed switches):

For actual application you would need a comparator with enable input and rescale values

Cheers

Klaus

Hmm, I think you lost me there. How can it sample the signal off of a sensor and store that sample value in a capacitor for later pickup? With the sampling time being a fraction of a nanosecond.

The procedure, hope nothing is wrong:

Use a micro output or whatever to charge the capacitor on the output of the comparator (node OUT) Hi-state the micro output (node OUT) Enable the comparator for 500ps (you need a fast comparator). The comparator slews the output to the input value. When node OUT is equal to the input signal, node OC rises. When OC rises, use that to Disable the comparator (needs perhaps level translation circuit) Use the OC rise to trigger the microcontroller to start ADC conversion.

Cheers

Klaus

That is a clever method. With comparators there is one problem though: When a very fast comparator sees little change or too slow a change on the input side it can burst into oscillation. If it doesn't see

Read the datasheet.

Cheers

Phil Hobbs

There is the 1-bit sampler thing, namely using a d-flop as an equivalent-time sampler, sort of a tracking ADC. It takes a lot of samples to build the waveform, but it's potentially cheap. A differential-input D flop, like an EL/EP52, can do that.

Yes, well I had always thought of doing it with a clocked comparator like the ADCMP572 etc., and the other input connected to a slow DAC. The tricky part is generating the clock pulse to the comparator, with accurately variable timing relative to the trigger input, but this might be easy if you control the stimulus to the circuit.

Another guy seems to have also thought of it:

Chris

Hello Joerg, If you are ready to accept, well, a significant waiver on the chip cost target, look at Hittite. A chip like the HMC760LC4B would probably nicely fit the technical specs (trak&hold with a 5GHz bandwidth, clock up to 4Gsps,

You can do it with an opamp also, just add a diode in the output

As for precision, route the reference to the input occationally, so you can do ratiometric calibration of offsets and propagation delays

Cheers

Klaus

I did it with tunnel diodes in 1969, inspired by a circuit in the GE Transistor Manual.

The advantage of the EL flop is that it's within Joerg's budget. The ADI comparators are expensive, and Hittite's pricing is insane.

I've look at opamps instead but that may be a few years off. There are reasonably priced ones with GBWs in excess of 15GHz but they are only stable at gains of 10 or so. That results in too low bandwidth for this application. In a few years that can be different.

Calibaration is not problem because test signals can be generated. That would calibrate the whole path.

It could do it but it would be a potentially long iterative process per sample time slot. An option may be to use some clever seek method instead of a stair-step ramp. Go to full, if not there go to half. If there go to 3/4, if not there go to 1/4, and so on. In my case the computational overhead would jinx it though.

Insane as in >$300 a pop :-(

You can do a feedback loop on the go/nogo decisions of the comparator/flipflop, so the thing becomes a tracking ADC of sorts. That's not too awful if the equivalent-time sweep is fairly slow.

If the clock rate is constant, the feedback loop could be just an RC or RLC from Q to \D, something like that.

The classic sampling-scope circuit can be built cheap. SRD, clip lines, 2-diode sampler, charge amp.

This got about 5 GHz bandwidth:

Might be an option, I'll have to think that through. The sweep time is several hundred times the sampling window and can be made constant.