You're missing the fact that the FET doesn't drop down to the low Rds(on) until you have a substantial amount of voltage drive. The datasheet measurement shows Rds(on) of 0.27 ohms, with Vgs equal to 10 volts.
Since you are tying the gate to the drain (24 volts), Vgs will be equal to the voltage drop across the whole FET. Under this load condition, Vds == Vgs == 4 volts, which is just barely enough to turn on the FET (the threshold voltage for 0.25 mA is spec'ed as being somewhere between 2 volts and 4 volts).
Under conditions of heavier load, the source voltage is going to sag even more... because you'll need a higher Vgs in order to turn on the FET to allow more current flow.
If you truly need the full 24 volts (or as close to no-load voltage as possible), you can't get there with your current circuit. It does not have sufficient voltage drive to the gate under conditions of meaningful load.
It's also vulnerable to failure downstream - if the load is shorted, and the gate is pulled all the way down to ground, you'll have 24 volts between gate and source, and this will exceed the FET's Vgs limit and might pop the gate insulation.
You have a couple of alternatives:
- Don't tie the gate to the 24-volt input. Provide a higher drive voltage... one which will be at least 5 volts (preferably more) above the drain voltage. You may need a voltage-boost circuit to generate a higher gate voltage supply. Make sure you clamp the gate to the source with a voltage limiter, somehow, so that the gate can't ever be pulled up more than 20 volts above the source.
- Use a different part topology. "High side" switches like this have often used P-channel FETS rather than N-channel, because you turn them on by pulling the gate down towards ground rather than up towards (and above) the drain/supply voltage. Again, remember to observe and ensure the Vgs limit.
Thank you very much for the input. It seems the P-channel approach is the way to go.
One more twist here. Let's say that I have a 24V application but the P-channel FET has a Vgs of +/- 20V.
1.) To turn the FET off if I connect the gate to 24V then Vgs = Vg - Vs = 24V - 24V = 0V.
2.) To turn the FET on the gate goes to ground. Vgs = Vg - Vs = 0V -24 = -24V. Here I have violated the +/- 20V Vgs. Is there a tricky way to work around this or do I just need to select a part that is at least +/- 24V?
One down-side to it is that P-channel power FETs with a very low Rds(on) are usually more expensive, and/or harder to find than N-channel equivalents.
Easiest workaround I know in this case is to connect the gate to the middle of a two-resistor equal-value divider. Connect the upper end to +24 and the lower end to your drive circuit.
When you're trying to drive the gate high, the gate is held firmly at
+24 (both your drive, and the fixed end of the divider are at that voltage) and the PFET is switched off quite firmly.
When you try to drive the gate low, your drive goes down to ground, the opposite end of the ladder is at +24, and the middle (and the PFET gate) are at +12. This gives you a Vgs of -12, which is well within the FET's limits and should also be enough to "turn it on hard" and bring its Rds(on) to a minimum.
The value of the resistors involves a tradeoff. Low values provide more gate drive current (faster turn-on/turn-off) but waste current in the ladder, and your drive circuit has to be able to source/sink this much current. High values are easier to drive, waste less power in the divider, but the FET switches more slowly... in extreme cases (high load) it might spend enough time in its linear region (partway on, partway off) to dissipate enough heat that this would be an issue. And, your switched load might or might not "like" slow turn-on.
Some years ago I used this trick "to extreme". I have a single DC control voltage which turns on, and turns off, a set of PFETs through resistor ladders of this sort, and each ladder has a capacitor to ground in its center (and then a small-value resistor feeding the FET gate). This creates a time delay for each PFET, based on the values of the ladder resistors and the delay capacitor. The PFETs switch some AC relays (solid-state or contact type) which switch on the final loads.
Net effect - thump-free power-up and power-down sequencing for my fairly complex stereo system. The amps aren't turned on until the source components and crossovers have powered up and their outputs are fully stable... then, a two-stage inrush-limited circuit turns the amps on "gently".
Also you can use the Zener as a limiter and overdrive some to get the switc hing time down. You can also use an inductor if you do that. Of course you only do such things under parametric duress... I man liie 50 amps at 500 Kh z...yes, a wee bit of drive optimization might just hit the spot.