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That's the "another possibility" I meant, above. The DAC only has to cover 1/4 of a sinewave, and you get the remaining wave portions by manipulating that.

To wit, the external logic walks the DAC up, then down, then kicks on the analog invert (x -1) function and cycles up, then down again. Then, back to the beginning.

That, here, would take about 5 chips & get you 32 samples per sinewave.

So, we've got several versions: 10 steps with one chip, 16 steps with three chips, or 32 steps for five chips. Or, as always, you could use a PIC :-)

I'm not sure what capacitance you're concerned about. The CMOS doesn't care--it's fast. Stray loading on the DAC? That should be pretty trivial at these frequencies. Besides, it works in your favor, filtering out the higher-harmonics.

-- Cheers, James Arthur

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Well if it wasn't, for heaven's sake don't post that here!

"To our wives and our girlfriends ... may they never meet."(*) --Old bachelor party toast.

(*)(P.S. I first typed that as "girlfiends" -- may those especially never meet!)

-- Cheers, James Arthur

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Or an 8-bit counter (e.g. '579), ROM, and DAC. 256 steps, three chips. ;-)

The synchronous counter is the limitation, here.

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Hmm I'm not sure either, now you mention it. I guess I'm (half) thinking of the output of the summing opamp. But, that's perhaps more a slew rate issue.

Anyway thanks for all the fun ideas!

George H.

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Hey, how about two 'HC4017's, driven out-of-phase. Clock one rising, one falling. That's 20 steps, two chips, dirt-simple.

-- Cheers, James Arthur

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Of course. Thanks be to you for the fun puzzle, for actually doing it, and then posting back. That's fun for everyone.

-- Cheers, James Arthur

Manufacturers, take note! If one can build/sell a RAMDAC ( old video part, intended to encode colors), how about a sine-table ROMDAC? Can you beat the price of ten $2 resistors, with 8-bit output converter?

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An FPGA. Hundreds of steps, one chip. Pick your poison. ;-)

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The way i see it matching will impact even more than odd and absolute value will impact odd more than even. But each will impact both. It is = a small enough dft that it is worth cranking it up in a spreadsheet.

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Come to think of it, I suspect staggered 'HC4017's doesn't work. Each output of "B" would straddle (be active during) two output states of "A", and the simultaneous equations fail. You'd need to buffer 'em so you could enable just one 'HC4017 at a time, which is messy & takes more chips.

So, it's either one 'HC4017, or a PIC. (Or a 555, details left as an exercise for the student.)

-- Cheers, James Arthur

We really need a 4017 with tri-state outputs. ;)

You could take advantage of the particular phase choice that George used, i.e. one phase is disconnected, and use a bunch of SIPO shift registers. Do a synchronous reset of all of them when the last stage goes high, and use an R-S flipflop to inject a 1 into the first stage when that happens, reset from the output of the first stage.

It would also need a missing pulse detector or something like that to make sure that it doesn't just sit there producing all zeros forever. You could get 8N+1 phases for about N+2 packages and 8N resistors.

Alternatively, adapting your folding trick, it might be possible to use a bunch of universal shift registers and just shuttle the 1-state back and forth from end to end, by changing the shift direction when it hits the end. That way you'd get 16N or maybe 16N-1 codes for N + 3ish packages and 8N resistors.

Fun.

Cheers

Phil Hobbs

art,

Hi Whit3rd, Are you making fun of me?

You can get 0.1% resostors from Sussumu for ~$0.20 each. George H.

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Dat's OK James, I'm still pondering your idea of multiple switching... using each resistor four times during a cycle. (I'm a bit slow so it takes me a while to digest what you are suggesting.) I must admit that the symmetry is appealing.

George H.

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The Apple start-up sound is called Sosumi- a legacy of the legal troubles between Apple and the Beatles. It was thought by their legal beagles to be a better choice than "Let it beep".

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The problem is that there's no linear mapping from that to a sine wave--for 2**N states you need 2**N outputs in order to be able to solve the linear system.

Cheers

Phil Hobbs

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This doesn't seem to be a sensible approach. My feeling is that the obvious way to synthesise a staircase approximation to a sine wave is with roughly equal amplitude steps, not that this saves you that many steps - the ratio is pi/2 to one. You design for an N-step approximation to a single quadrant, with N resistors and N SPST switches plus one SPDT - the extra switch changes the polarity of the source voltage from 180 dgrees to 360 degrees - and drive the switches from a programmable logic device which can count up to roughly 2.pi.N and decodes the counter output to drive the N+1 switches. The resistors wouldn't be identical, but their resistances won't be wildly different either.

-- Bill Sloman, Nijmegen

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Well I stuck a switch cap filter on the output. (LTC1063, I know only

I clocked it at 16 times the stepped sine wave so the 3dB point was

And after it.

The second harmonic goes up more than 10dB! And there is all this other =91fluff=92 at low frequency. Some new peak stands up at 2.5 kHz. I moved the 3dB point up to 3.2kHz and the 2nd harmonic was a few dB better... the weird signal at 2.5kHz moved out to 5 kHz? Not sure I like switched cap filters. We used the same SC on a different project and it also added =91out of band=92 curd... at similar levels.

I=92ll try an analog multi pole Butterworth. Maybe a Sallen-Key.

George H.