pcb trace inductance

It uses the Sonnet 3-D solver which has been around 35 years that I know of. Better late than never I guess.

Thanks, John! Good one! ...Jim Thompson

-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

Thinking outside the box... producing elegant solutions, by understanding what nature is hiding.

"It is not in doing what you like, but in liking what you do that is the secret of happiness." -James Barrie

Matches the age of the GUI

Cool it can do planar inductors? Have you tried it for that?

It's a heap easier to use than Sonnet.

Yes, it does; it's shown in the menu. I haven't used that myself. I prefer discrete parts that are small and easy to change.

I have considered using stacked planar coils as high-voltage isolators, but haven't actually done any products that way.

It seems a popular thing to do on high volume consumer items that have to process RF yet hit a $79 price point, PC GPU boards are often covered in abstruse squiggles and crop circles

That's length matching. If they could get away without it, they would shave the few cents off the thing (in size or copper).

Those interfaces are amazingly tolerant of timing errors, impedance mismatch and board losses, but they can't do it all, especially at modern clock rates.

(I suppose as soon as someone reinvents RAMBus with modern gigabit lanes, we'll be set, as far as length matching goes. I wonder if the only thing stopping them is latency? All that buffering, serdes and clock recovery takes a lot of time, after all.)

Tim

It's very difficult to get a trace much under 30 ohms, much over 150 ohms, or a velocity factor very different from 0.8 or so. This puts the inductivity right around 1.257 uH/m * (Zo / 377R) / 0.8 or ballpark 0.5 uH/m. 1nH/mm is a good worst-case starting point.

Then measure the length of the route, include ground return path if also routed (or poorly stitched), and there you have it.

Pathological cases obviously vary. Not really pathological, it's just proportional. A 10cm wide power pour has a Zo of, say, a few ohms, and near nil inductance.

Working example:

I was building another power supply, with about 20nH stray from filter caps to half bridge. (The path length is, yup, just over an inch round trip.)

The SuperJunction transistors ring like crazy at 60MHz. The risetime is so fast, it excites everything it can. (It's not an active oscillation -- the gate drive is fairly weak, and ferrite beaded. The ringing is caused by the opposite side switching on.)

At a switching frequency of 300kHz, I can't use ferrite beads on the drain to dampen the ringing. I mean I can, but it only works for a few seconds, then the bead thermoregulates at ~100C (NiZn type, so the Tc is kinda gross). I've made a low temp Metcal tip, not a damper!

Tim

I wonder how long it will be before some bright spark working on Kicad or similar OSS decides to export the PCB layout to a field solver, and take the output from that to build a SPICE netlist with the predicted parasitics (lumped impedance, time delays, etc).

It doesn't seem like it would be that difficult to do.

Clifford Heath.

Uncertainty in the part models might make that not work well.

There is high-end PCB sim software, fabulously expensive and a big deal to set up. Mostly RF. I don't know how well it works.

So what? Board dynamics are what's in question. Obviously, you need to make sure your parts are right.

For most boards it's not very useful, really -- you need maybe a dozen nets, not the whole board. Or for signal quality, just use whatever analysis tool you have handy (e.g., Altium has this), make sure you have IBIS models for everything.

Of course, you can't use IBIS models in SPICE and vice versa.

Ansys, among others. Starts in the five digits, and you better be willing to spend as much in labor setting up your models and divining results from it!

Tim

Yeah, shouldn't be too hard: take the PCB file, extract the netlist, take all copper objects, pad stacks and layer stackup and extrude a 3D model from that, then dump that into the boundary conditions needed for, say, FEMM, or anything fancier.

Would be cool to have skin effect as well, but that's unlikely. That gets very intensive, very quickly, in any kind of FEA.

Tim

Sure you can. That's one of the services I offer. See my home page.

-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

Thinking outside the box... producing elegant solutions, by understanding what nature is hiding.

"It is not in doing what you like, but in liking what you do that is the secret of happiness." -James Barrie

I don't sell bare boards. It's easy to figure out trace impedances, but it's really difficult to simulate fast parts. Mostly I test them, and sometimes lay out a proto board.

Generation of SPICE netlists for traces of distributed filters has already been done. Check out "Automated Electronic Filter Design = With Distributed Filter Emphasis" published by Springer last year.

I'm sure it has, but not in Eagle, KiCAD, or something equally easy to obtain. And my thought is to incorporate the traces into an active design.

Thanks for the pointer.

Clifford Heath.

I have used Saturn for some time and enjoy its?s features and accur acy especially on reduction of effective dielectric constant with rising f.

Some people are aware that a 10x10cm track has that Nam inductance as 1x1 m m

Thanks, that is a nice set of tools. They even offer design services in case the work load becomes too heavy.

Link: