There are some dynamite isolated d-s ADCs around. You give them a 20 MHz clock and they output a single clocked logic level whose duty cycle expresses the analog input.
The data bit is "decimated", really averaged, to give an integer analog value. That is usually done in an FPGA, with a sinc3 filter or something.
I'm wondering of such an ADC can be used without an FPGA.
I guess an analog lowpass filter and a regular low-speed ADC might work, at moderate accuracy.
Or, more radical, use the SPI port of a uP to gather up bits and let software take over. A 125 MHz ARM has a lot of compute power.