This is PADS-PowerLogic version 5.0.
I have a clock net SCKB that runs here and there. I decided to add a termination resistor to ground, so I did that, and did a forward ECO file to the PCB. The resistor is added, but the reference designators of two unrelated ICs are swapped in the ECO file too, and this rips out their nice PCB routing.
If I add the resistor, and ground one end, but don't touch SCKB, the ECO is OK.
If I add any new part to the SCKB net, it messes up.
Except that if I run an unused pin from a nearby uP chip to SCKB, the resulting ECO is ok.
THEN I can add the terminator, OK!
Then if I leave the terminator and remove the uP connection, the problem is back!
The other problem we're having with this design is that if we export a schematic netlist, PCB refuses to do a netlist compare. It complains about an end-of-file or something. The schematic output ascii netlist looks OK to us, no weird control characters or anything.
So it looks like the schematic is corrupted somehow. An ascii in-out cycle doesn't help.
PADS is usually stone-cold reliable. This is weird.
Any suggestions?
John