Hi all, I finished off a William Goldman* book last night and picked B. Pease's "Trouble shooting analog circuits" of the shelf.
He does a little active probe circuit.
So why is there the second pnp follower? Why not just take the output from Q3?
George H.
*I'm not sure I like W. Goldman's books but I find his writing compelling.
Hi George
The probe is DC-coupled, so the Q3 Vbe (and TC-drift) will be more of less "nulled" by the Q4 Vbe (and TC-drift).
It seems that the goal is to get zero volt output for zero input.
Glenn
Attempting to cancel Vbe drift. ...Jim Thompson
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I love to cook with wine. Sometimes I even put it in the food.
What Glenn and Jim said plus -- didn't he say so in the text? I would have expected him to justify every part in the circuit, given how few of them there are.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Got it, thanks Glenn, Jim.
Nah, there's nothing in the text about how it works. But I sorta get the Q2 as current source/ offset adjust. I could sometimes use a low capacitance probe.
He does claim that it only has 0.29 pF of input C. I wonder how that works. The jfet's look to have at least a few pF
George H.
Oh, _that_ should be obvious..to cancel out the DC offset caused by Q3.
It's a source follower. The Miller Effect works for you in this case: the capacitance is equal to Cgs * (1 - Av) + Cgd (if I have my math right). Since it's a source follower, Av is almost 1, which means that Cgs gets multiplied by a teeny number.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
The intent there is to run the fet at Idss, zero dc offset. And the fet TCs sort of cancel too.
Really serious fet probes bootstrap the drain too, to cancel most of Cgd.
Nowadays, a good fet opamp can be a better choice. ADA4817 maybe.
-- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation
OK thanks for the "hint". I know of the Miller effect, but I don't really "know it", if you know what I mean. I thought it was Cgd that got "Millered". (I'm mostly analogizing to the base-collector capacitance in a bjt.) I'll got read some.
George H.
OK but that would not look nearly as intimidating as a probe with a bunch of transistors and R's hanging off it.
George H.
Phemts would be good for really fast, low capacitance probing, instead of klunky old jfets.
Take a look at the schematic of a Tektronix 7A13 plugin. It has hundred-volt overload capability and instant recovery at 100 MHz. The bootstraps and tweaks are amazing.
The old W and Z plugins were impressive, too.
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
ng.
.Worst case tolerance on the "cancellation" seems to be +/-200mV - the data sheet Vbe's at 10mA are both 0.65V to 0.85V. You'd expect both to be mid-ra nge, but the distribution is a trifle unpredictable. If they meet the spec by design you'd expect 200mv to be something like 6 standard deviations, an d the most likely offset would be down to about 50mV, while if they test an d discard parts that don't meet the spec it would be more.
-- Bill Sloman, Sydney
You forgot that I live on the trailing edge of technology. If it's old and klunky and soon to disappear, I should learn about it as soon as possible. :^)
Seriously, too fast can be a problem. I mostly use an old 60MHz TEK DSO* so the bandwidth is fine. Even 1pF Cin would be over an order of magnitude improvement.
George H.
*one good thing is that it's less noisy than other (cheap) DSO's
Q3.
a sheet Vbe's at 10mA are both 0.65V to 0.85V. You'd expect both to be mid- range, but the distribution is a trifle unpredictable. If they meet the spe c by design you'd expect 200mv to be something like 6 standard deviations, and the most likely offset would be down to about 50mV, while if they test and discard parts that don't meet the spec it would be more.
OK thanks, I guess I should order some jfets and make it. (The 100 ohm pot is a bit of a nuisance... can I run it a bit leaner? higher resistance.) You can tweak the offset, so the next big thing is the tempco. (as Glenn and Jim said.) Lots of times I don't care about DC..
George H.
That's the classic Miller capacitance, Cgp * (1 + gain) gp = grid:plate
Cgs can be reduced by having the source follow the gate. That's sort of an anti-Miller effect. At a follower gain of 1, Cgs disappears.
Cgd can be reduced by bootstrapping the drain from the source voltage, which itself is following the gate. So gate capacitance can be driven almost to zero.
-- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation
Yeah.. I got it, thanks. (I was reading in AoE last night.... the FET chapter even has the jfet follower as scope vertical amplifier input... so many circuits that I've looked at.. but unless you try 'em they are not really "yours".)
George H.
I would expect the variant for a particular source nowadays to be quite a bit less for discretes. Modem process are much tighter controlled than 35 years ago, from whence the data sheet probably originated for the
2n3904/2n3906. Its reasonable to expect a Vbe to be within +/-10mv to +/-50mv over all processes corners for ics. I have yet to see one specified larger than 50mv for some time. 25mv seems an average, but 10mv for the better processes.Kevin Aylward B.Sc.
Phil Hobbs is the Master Bootstrapper. See his book and his web site.
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
It is possible to cascode couple an emitter/source follower:
See fig. 7b:
Glenn
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