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XILINX CoolRunner-II CPLD's allow macrocell FF's to toggle on both clock edges - this feature is called cool clock. Some previous MACH devices also had these capabilities.
The problem of this technique is, that a clock's duty cycle is not as stable as it's period time.
MIKE
-- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho !
A flip-flop (Eccles-Jordan circuit) is basically two transistors and some positive feedback. The output has only two stable states (ON and OFF) and the rise time is independent of cruft on the trigger (input) signal. So, it makes a really fine digital element, embodying some of the requirements of good binary logic without lots of parts.
A modern flip-flop is usually a fancy master-slave type or even clocked D type... and seems not to do what you want.
If you want something to operate on either kind of transition, you might (this is a crufty hackish thing to do) consider using an XOR gate and feeding it your signal straight into one input, and through a delay (like a couple of inverters) into the other input. The XOR will pulse whenever there's a transition.
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