question on 8085.

Because the earliest PMOS ICs had passive pullups. Also TTL thresholds are nearer 0V than 5V. After that, we just kept doing it.

Because that ensures that the internal clock is 50% duty cycle.

Conventiopn. Plus, the active low matches the input polarity of RAMs and EPROMs.

Helps to ensure 50/50 duty cycle. Besides 4 MHz sounds better than 2 MHz. Think of the 8080 devices. They were advertized as 18 MHz, but actually ran at 2. The 18 made it sound like they were 9X faster than the 6800.

You should drop back and ask why you are asking these questions.

Because it sure sounds like a homework question.

Otherwise, you'd be asking "why do some things use active low?".

Michael

messagenews: snipped-for-privacy@a75g2000cwd.googlegroups.com...> CAN ANYBODY HELP ME. FOR THE QUESTIONS THAT

Plus, the active low matches the input polarity of RAMs and

which goes back to TTL being much better at sinking than sourcing

sounds better than 2 MHz.

It is probably made with latches and need to generate a two-phase non-overlapping clock to drive them. Or it has multiple state per machine cycle, for e.g. memory accesses.

-Lasse

As I recall, some of the timing was referenced to the positive clock transition, and some to the negative going; so, duty cycle was not arbitrary. I don.t think it had multiple states per 1X clock, but a 0 wait memory cycle was several clock cycles long. Ditched the data sheet at least

Tam