tee trace

A piece of kapton tape and some copper tape on top sounds like a plan - but I have never done it, just witnessed a guy do demos with that sort of thing.

John - a possible approach: the higher the dielectric constant on which a conductor sits, the lower it's impedence. So, maybe some tape on top of your errant conductor.

Hul

snipped-for-privacy@highlandsniptechnology.com wrote:

mandag den 13. december 2021 kl. 16.38.35 UTC+1 skrev snipped-for-privacy@highlandsniptechnology.com:

so add an extra layer for a ground plane close to the microstrip, but leave it blank where you need low capacitance

standard pcb expect for the special stackup and no extra production steps

It's already a 6 layer board. Here's the trace, running from the IC to C28. I want it to be 25 ohms but can't make it wide enough. Adding the coplanar waveguide grounds only helped a little.

I could TDR a microstrip and stick something on top, like a piece of FR4 or maybe even just some epoxy or something. Yes, I'll try that just to calibrate my expectations.

If it is microstrip, you've routed it on the surface of the board. If you used buried stripline the impedance will be lower for the same trace width.

Burying two of them (with ground plane in between) and putting them in parallel would halve that impedance. It's two vias - one at each end - but you should be able to figure that in.

tirsdag den 14. december 2021 kl. 02.36.19 UTC+1 skrev John Larkin:

is is very short and looks you could easily make it shorter

Yeah, he doesn't say what he's doing. I wonder if he's solving the right problem.

That trace is about 0.12" long, roughly 20 ps, but I've made it about as short as I can. There are all sorts of other parts around.

The RF boys measure flatness in dBs but we need PPMs. This is for a laser modulator for people with extreme expectations.

Chances are it's the 11GHz/25ps laser diode driver from last week, and he wants to manage the impedance from the die to the coupling capacitor, at least.

John, you need to use a field solver.

CH

I can easily calculate the trace impedance, but I want 25 ohms and that's not practical on this layout. The source chip is basically an

ATLC could calculate a microstrip with a slab of dielectric added on top. But ATLC is basically a 2D analysis and life is 4D : X Y Z T.

And I don't have device models, which I'd need for a serious simulation. Modifying trace impedances up is easy with an x-acto knife. Maybe piling on dielectric or the shark fin would let me tune impedances down.

Am 14.12.21 um 05:27 schrieb snipped-for-privacy@highlandsniptechnology.com:

You could use 2 parallel coplanar wave guides on different layers or load the top one with additional vias, or use a higher eps-r material on the top level.

This here is harmless.

In that 10 GBPS XFP transeiver from 15 years ago the laser diode had to float mechanically, so we used a Kapton tape to connect it. It also had to switch the layer.

The RF boys used a lot of HFFS simulation time to get it right. Simulia CST, Keysight EMPRO, HFFS or Sonnet are your friends.

Gerhard

HFSS, sorry

oh article must contain real content

Vias are death at these speeds.

Most microwave laminates are lower Er than FR4, and are exotic and expensive.

Eval boards for exotic amps are usually very skinny coplanar waveguide on very thin microwave laminates, and assume external bias tees and DC blocks and manually tweaked power and bias supplies.

Unfortunately, we don't have device models for the critical parts, and certainly not nonlinear Spice models. So it's faster to etch boards and futz with them than buy and learn and run and fight licensing issues on expensive simulators.

We're doing large-signal high precision pulses with RF parts. The RF specs are only suggestive and often deceptive.

I suspect that a fin would be disappointing for that use--the fringing fields aren't that different unless the fin is tall, and in any case they have to take a long path in air before reaching the ground plane.

Thin copperclad Kapton tape would probably work for this. There will be issues at low frequency because of the capacitive impedance in series with the return current from the top copper layer, but for a trace that short, you don't care about low frequency reflections very much. It should be pretty doable if there aren't a lot of top-level traces nearby to cause crosstalk.

Cheers

Phil Hobbs

I should have cut away solder mask so I could hang some tiny caps between the trace and the cpw grounds, to pull the impedance down, or possibly use resistors for damping. The mask could be scraped.

tirsdag den 14. december 2021 kl. 05.27.11 UTC+1 skrev snipped-for-privacy@highlandsniptechnology.com:

just move C28 to the left, right up against the IC ?

Exactly what I told him also. Anything else is just a stab in the dark. It's not like you can probe it afterward to see why it's not working well.

CH

Perhaps you should connect the current source in an expedient way, with two transmission lines; one to the laser, one that is a 'stub' onto which you can hang loads, or etch to length. A field solver can guide the crafting of that stub. Artistically crafted metal on a PCB is a powerful solution technique, at 20 ps.

Esp. when the problem at hand has nothing to do with nonlinearities. This is a 2.5 or 3D electromagnetics problem. And that includes the TO-whatever box of the laser.

It could be co-simulated with ADS/EMpro, ADS taking care of the spice-like parts. pHEMT support/modelling is probably better in (ADS or similar) than in LTspice.

cheers, Gerhard