Rise time of standard FR4 vs low loss laminates

Jun 14, 2023 Last reply: 3 years ago 6 Replies

Hi



I am working on a design where we have a fast rise time of a signal, below 1ns and above 50V. We want that fast risetime, part of the requirement.



The topic has come up of the selection of the laminate. So what will be the difference between risetime of astandard FR4 vs low loss laminate (Rogers 4350)?



The dielectric constant is about 4 for standard FR4, while 4350 has about 3, so less capacitance in a 4350 design, which will load the risetime less due to less trace capacitance. But then, since the dielectrics is different for the 4350, we need to change the width to get the same characteristic impedance, so it might even out?



My guess is that the difference is small compared to the sub 1ns risetime.



Page 54 of this presentation has some data:



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But seems, it does not include standard FR4, whatever that is....



Regards



Klaus


1 ns is not especially fast.

Sure. Design a 50r trace either way.

How long does the trace have to be? What impedance?

1 foot of 50 ohm microstrip would look almost perfect with ordinary FR4 and 1 ns drive.

Here's a 3" long 50r microstrip trace on FR4

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The scope rise time is around 30 ps.

I played with some Isola lam and it was a bit better than FR4.

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Am 14.06.23 um 02:07 schrieb Klaus Vestergaard Kragelund:

1 ns is not fast. That's nervous DC. :-)

This board is 80 mm long. The intentionally complicated trace is somewhat longer, the SMA decals are suboptimal for the Rosenbergers that I used. Optimum trace width for 50 Ohms is

11.5 mil according to the JLCPCB calculator. Board is 4 layers. That requires some cutouts on on the inner layers. I used only 10 mils width to see what I can get away with. The el cheapo multilayer boards are maybe $/€ 1 per pop excluding postage. <
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The TDR shows that the impedance is a bit higher than 50 Ohms for the 10 mils.

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The risetime after the wrong SMA decal, port savers, Semi rigid is still better than 50 ps. HP54750 / Agilent 54754A 18 GHz differential TDR/TDT.

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Gerhard

Very interesting measurements, thanks a lot. I would like to be able to calculate it, but I guess that is not that simple.

We did this at Cambridge Instruments in the late 1980's. We were producing complementary pulses that swung from +7V to 0V and -7V to 0v - 140mA into 50R (which got warm but not for long).

The rise and fall times were about 200psec, and full width at half maximum was 500psec +/-10%. In reality the pulse rounded off a bit and the 500psec pulse was bodged to swing up from -5V to 0V and down from +5V to 0V,

FR4 worked fine. It got a bit hot and eventually we moved to poly-imide bonded glass fibre which got just as hot but didn't discolour and worry the users.

We shipped quite a few of them - several dozen over the years

We eventually got serious and put the pulse driver onto a Rogers board made with PTFE bond alumina which had a lower dielectric constant so needed wider traces for a 50R characteristic impedance and let me put some 150R characteristic impedance tracks for the bodge circuits.

It wasn't any faster - the limitation was clearly in the wide-band bipolar transistors we were using. I had some thought about higher current parts, but didn't get to build anything

The problem with resin bonded glass fibre is that it is lumpy and puts small ripples on the transitions. The PTFE alumina was much more uniform, but now-where near as strong, and we put the fast bits on a small daughter board.

If you get serious you run into the problem that surface traces are intrinsically dispersive. Buried micro-strip lines aren't, but they are appreciably narrower for the same characteristc impedance.

We had an ambition to get down to a 100psec wide pulse and did a little bit of thinking about the board we'd want for that.

Skin effect probably dominates dielectric loss for shortish digital signals, but it's still a lot easier to measure than to calculate.

If your signals are digital, with a roughly Vcc/2 receiver threshold, some special cases are involved. A modest amount of trace loss results in a fast rise and some drool on top, and the receiver will trigger on the fast part and ignore the drool. The result is a bit of pattern-dependent "deterministic" jitter, intersymbol interferance, which usually doesn't matter.

Fast stuff like PCIe can use adptive equalization and cheap PC boards.

People like to measure 20/80 rise times on fast stuff instead of the usual 10/90, to ignore the drool and get better numbers.

Fancy dielectrics are useful for microwave stuff, to keep up filter Qs and keep noise figures down, but are seldom worth the cost for digital circuits. The really low loss lams are soggy and have bad trace adhesion.

My coffee cup is empty! Gotta go.

I typed an answer very early this morning but there was an SMTP error when posting it, probably lost.

Am 14.06.23 um 02:07 schrieb Klaus Vestergaard Kragelund:

1 ns is just nervous DC.

I have made a test board using JLCPCB's 4 layer el cheapo process. The board is 80 mm long, the trace with the funny bends is a little bit longer. About $/€ 1 per board + postage.

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The trace is only 10 mil wide, 50 Ohms is 11.5 mil. That can be seen just so on the TDR result. I wanted to see what I could get away with. Also, the part decal does not fit exactly the Rosenberger SMA connectors. The Rosenberger SMA has a two screws flange.

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The setup is this: <

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The yellow trace is the TDR result on Agilent 54754A differential TDR plug in. The line is 2 div right of the middle, the 2 SMAs are slightly inductive, line impedance is a tad higher than the precision line in the plug in, as was to be expected.

This here is the risetime after the travel tru the line: <

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Still 50 ps or better including the semi rigid, port savers, suboptimal SMA connections and FR-4.

Gerhard

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