Suppose I have a P-channel enhancement mode MOSFET set up for high-side switching (Source=positive rail, Drain=load to ground). I know that when the gate is sufficiently more negative than the source, then the FET will conduct. But my quesiton is about what happens when the FET is supposed to be off. Specifically, what happens if the Gate is biased a few volts more positive than the source? That forward-biases the internal Gate-Source diode, and some current flows there. But is it safe to say that none of that current flows to the drain? For my application it is important that there be essentially no drain current, even if the gate is biased more positive than the source.
- posted
14 years ago