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Optoisolators

I'm hooking up the desat detectors on my induction heater. I'm using PV702V optos for coupling the desat signal to the shutdown latch, both high and low side, for symmetry's sake. I've got half an LM393 doing the desat detection itself (what a pretty slope it sees from these MOSFETs ;), which means I can only pull a few miliamperes for the error signal, in this case a 4.7k resistor from +18V. I have this ANDed, with a diode, to the gate signal, so that only when drain is above the desat threshold AND the gate is positive, a positive signal is sent out. Good so far. But pushing this into the opto's photodiode directly is really crappy, so I've got an emitter follower to the diode, with 1k current limiting resistor. That's a maximum of

10-15mA or so into the diode and should provide reasonable response, no?

It seems to work, with the phototransistors paralleled pulling on a 2.2k resistor. I can't really make a go/no-go decision with MOSFETs though, what with the Rds(on) characteristic.

But that said, what the hell am I supposed to do with the base on these optos? And why does the high side waveform tickle it (as near as I can tell)? Seems rather shitty to me that what little capacitive coupling is in these things is able to tweak the phototransistor by a whole miliamp or so.

Tim

-- Deep Fryer: a very philosophical monk. Website:

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Reply to
Tim Williams
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what

Why Not?? "Too High D-S Voltage" is A Failure whatever the reason, 7-10 V for a few usec when supposed to be On is good IMO.

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so.

Ground it with a suitable resistor - the lower the value, the lower the CTR (and the lower the sensitivity to other things). Between 470k and 470R is about right ;-) i.e the lowest value that still gives some margin on the lower-bound CTR from the datasheet is what you want.

Reply to
Frithiof Andreas Jensen

you can, its just a bit more arbitrary. Vds = 75V while Vgs > Vth would, for example, be a good time to desat.

Hi Tim,

sometimes lopping off the base pin can help. Or use an opto with a built-in faraday shield, eg sfh6345. pretty much any "gate drive" opto has such a shield.

ultimately it'll be CdV/dt. you can measure dV/dt pretty easily, and measuring the resultant output current will give you an idea of the magnitude of the problematic capacitance. and yeah, bunging the current up the base of the bjt really makes things worse.

Cheers Terry

Reply to
Terry Given

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