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need help on PSK demodulation solution

Hi everyone, I have to build a PSK commutation system. The carrier is

1MHz or 2MHz and the required date rate is 10-100Kbps. I can use a DDS AD9835 to produce the transmitter PSK/DPSK/DQPSK signal. However, I find that it$B!G(Bs a problem with the demodulation design. Generally speaking, there are two demodulation methods: non-coherent and coherent demodulation. With non-coherent demodulation, it has a delay module for the reference signal because it is simply a delayed version of the received signal. My question is how to implement the delay without FPGA/DSP chip? Is there any circuit or IC can do this? With coherent demodulation, a carrier recovery circuit is need (Costas loop, etc), is there anyone can recommend appropriate chips (such as phrase detector and VCO)$B!)(BI found that many demodulator chips do not work at a low frequency like this.
Reply to
X.Y.
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Why do you "have to build a PSK commutation system"? Sounds like a school assignment.

Why not FM?

You can implement the delay as an LC filter... see Williams' filter book.

John

Reply to
John Larkin

Why not DSP? By the time you get your analog circuit done you'll have spent almost as much time as you would to get it going in a small FPGA or CPLD; by the time you finish your first obligatory sales-driven change to the circuit you will have doubled this time with an analog circuit and increased it by only 10% with a digital one -- and the digital one will be easier to ride herd on in the factory.

Noncoherent demodulation works well in a DSP context where you convert the signal down to baseband with a complex (I-Q) downconverter. You could implement the necessary 5-50 microsecond delay using analog all-pass filters, but you'd have to do it in both channels, you'd have issues with controlling the filter parameters over temperature and manufacturing variance, and when you were done you'd have a complex multiply to contend with. This is _not_ the simplest approach to take!

There are any number of options you can use for a phase detector, depending on what your constraints are. If you're getting a good strong carrier then you can just clip it to logic levels and use an XOR gate for "multiplication". Indeed, you can square the carrier (i.e. x^2), filter it, then clip it to get your phase reference, and use a 4046 or similar PLL chip for carrier recovery.

Check the amateur radio literature for ways to do this -- there are a number of PSK demodulators out there to look at.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" gives you just what it says.
See details at http://www.wescottdesign.com/actfes/actfes.html
Reply to
Tim Wescott

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