I need help on ADS1217

The comment that 'the hardware is ok' (even when done in English as a second or third language) is a giveaway that all may _not_ be right.

You don't tell us the complete application, what you are controlling it with (processor, OS if any, interface details), nor what it is acquiring (or supposed to be acquiring).

If you want help you'll have to state the problem explicitly and preferably also post a scematic to a.b.s.e or use an ascii schematic tool to give us a clue.

The device is perfectly straightforward, but as with all A-D converters has quirks that can trip you up quickly and spectacularly.

So - give us some details, or expect no help.

Cheers

PeteS

Forgive me for my poor english

I use ADS1217 for a data acquire system. I use optical coupler for SPI interface. And I have get the right data before. Now I modify the code ,and I can't make it work properly.

The CPU I use is MSP430F149,I use IO port to stimulate for SPI interface.

The Programe is like this

#define ADS121X_SETUP_REG 0 #define ADS121X_MUX_REG 1 #define ADS121X_ACR_REG 2 #define ADS121X_IDAC1_REG 3 #define ADS121X_IDAC2_REG 4 #define ADS121X_ODAC_REG 5 #define ADS121X_DIO_REG 6 #define ADS121X_DIR_REG 7 #define ADS121X_DEC0_REG 8 #define ADS121X_DEC1_REG 9 #define ADS121X_OCR0_REG 10 #define ADS121X_OCR1_REG 11 #define ADS121X_OCR2_REG 12

#define ADS121X_FSR0_REG 13 #define ADS121X_FSR1_REG 14 #define ADS121X_FSR2_REG 15

#define ADS121X_RDATA_CMD 0x01 #define ADS121X_RDATAC_CMD 0x03 #define ADS121X_STOPC_CMD 0x0f #define ADS121X_RREG_CMD 0x10 #define ADS121X_RRAM_CMD 0x20 #define ADS121X_CREG_CMD 0x40 #define ADS121X_CREGA_CMD 0x48 #define ADS121X_WREG_CMD 0x50 #define ADS121X_WRAM_CMD 0x60 #define ADS121X_CRAM_CMD 0xc0 #define ADS121X_CSRAMX_CMD 0xd0 #define ADS121X_CSARAMX_CMD 0xd8 #define ADS121X_CSREG_CMD 0xdf #define ADS121X_CSRAM_CMD 0xe0 #define ADS121X_CSARAM_CMD 0xe8 #define ADS121X_SELFCAL_CMD 0xf0 #define ADS121X_SELFOCAL_CMD 0xf1 #define ADS121X_SELFGCAL_CMD 0xf2 #define ADS121X_SYSOCAL_CMD 0xf3 #define ADS121X_SYSGCAL_CMD 0xf4 #define ADS121X_WAKEUP_CMD 0xfb #define ADS121X_DSYNC_CMD 0xfc #define ADS121X_SLEEP_CMD 0xfd #define ADS121X_RESET_CMD 0xfe

#define ADS_SCK_LOW P1OUT &=3D(~BIT4) #define ADS_SCK_HI P1OUT |=3D BIT4 #define ADS_D_HI P1OUT |=3DBIT3 #define ADS_D_LOW P1OUT &=3D(~BIT3) #define ADS_DIN P1IN & BIT2 #define ADS121X_CS_LOW P1OUT &=3D(~BIT5) #define ADS121X_CS_HI P1OUT |=3D BIT5 #define ADS_RDY P1IN & BIT6 #define DAC_CS_LOW P1OUT &=3D(~BIT7) #define DAC_CS_HI P1OUT |=3DBIT7

void delay ( INT16U delay_tmr ) { while ( delay_tmr ) delay_tmr --; _NOP(); }

void ads1217_cs_low(void) { delay ( 100 ); ADS_SCK_LOW; delay ( 100 ); ADS121X_CS_LOW; delay ( 100 );

} void ads1217_cs_hi(void) { delay ( 100 ); ADS_SCK_LOW; delay ( 100 ); ADS121X_CS_HI; delay ( 100 ); }

INT8U ads1217_so ( INT8U data ) { INT8U shift,tmp,result; shift =3D 0x80; result =3D 0x00; for ( tmp=3D0;tmp>1; } return result; }

void wr1217_reg_buf( INT8U reg_adr,INT8U *cmd_buf,INT8U lenth ) { INT8U tmp;

ads1217_cs_low(); delay ( 100 ); tmp =3D ADS121X_WREG_CMD+reg_adr; tmp =3D ads1217_so ( tmp ); delay ( 100 ); tmp =3D lenth -1; tmp =3D ads1217_so ( tmp ); delay ( 100 );

while ( lenth ) { tmp =3D ads1217_so ( *cmd_buf ); delay ( 100 ); lenth --; cmd_buf ++; } ads1217_cs_hi(); }

void wr1217_reg ( INT8U reg_adr,INT8U cmd ) { INT8U tmp; ads1217_cs_low(); delay ( 100 ); tmp =3D ADS121X_WREG_CMD+reg_adr; tmp =3D ads1217_so ( tmp ); delay ( 4000 ); tmp =3D 0x00; tmp =3D ads1217_so ( tmp ); delay ( 4000 ); tmp =3D ads1217_so ( cmd); delay ( 4000 ); ads1217_cs_hi(); }

void wr_ads1217_reg( void) { INT8U tmp; ads1217_cs_low(); tmp=3D ads1217_so( ADS121X_WREG_CMD); delay ( 2000); tmp=3D ads1217_so( 0x07); delay ( 2000); tmp=3D ads1217_so( wreg[0]); delay ( 200); tmp=3D ads1217_so( wreg[1]); delay ( 200); tmp=3D ads1217_so( wreg[2]); delay ( 200); tmp=3D ads1217_so( wreg[3]); delay ( 200); tmp=3D ads1217_so( wreg[4]); delay ( 200); tmp=3D ads1217_so( wreg[5]); delay ( 200); tmp=3D ads1217_so( wreg[6]); delay ( 200); tmp=3D ads1217_so( wreg[7]); delay ( 200); ads1217_cs_hi(); delay (4000); } void rd_ads1217_reg( void) { INT16U tmp; ads1217_cs_low(); delay ( 200); tmp=3D ads1217_so( ADS121X_RREG_CMD); delay ( 2000); tmp=3D ads1217_so( 0x0f); delay ( 2500); rreg[0]=3D ads1217_so( 0x55); delay ( 200); rreg[1]=3D ads1217_so( 0x55); delay ( 200); rreg[2]=3D ads1217_so( 0x55); delay ( 200); rreg[3]=3D ads1217_so( 0x55); delay ( 200); rreg[4]=3D ads1217_so( 0x55); delay ( 200); rreg[5]=3D ads1217_so( 0x55); delay ( 200); rreg[6]=3D ads1217_so( 0x55); delay ( 200); rreg[7]=3D ads1217_so( 0x55); delay ( 200); rreg[8]=3D ads1217_so( 0x55); delay ( 200); rreg[9]=3D ads1217_so( 0x55); delay ( 200); rreg[10]=3D ads1217_so( 0x55); delay ( 200); rreg[11]=3D ads1217_so( 0x55); delay ( 200); rreg[12]=3D ads1217_so( 0x55); delay ( 200); rreg[13]=3D ads1217_so( 0x55); delay ( 200); rreg[14]=3D ads1217_so( 0x55); delay ( 200); rreg[15]=3D ads1217_so( 0x55); delay ( 200); delay ( 200); ads1217_cs_hi(); delay ( 200); }

INT32S rd1217_data( void ) { INT32S s32tmp; INT8U utmp,utmp1,utmp2;

s32tmp=3D0; ads1217_cs_low(); delay ( 200); utmp =3D ads1217_so(ADS121X_RDATA_CMD); delay (6000);

utmp=3Dads1217_so(0x55); delay ( 200); utmp1=3Dads1217_so(0x55); delay ( 200); utmp2 =3Dads1217_so(0x55);

s32tmp =3D s32tmp + utmp; s32tmp =3D s32tmp *256 +utmp1; s32tmp =3D s32tmp *256 + utmp2; delay ( 200); ads1217_cs_hi(); return s32tmp;

} void ads1217_init( void) {

INT16U tmp;

ads1217_cs_hi(); delay ( 2500); tmp=3D ads1217_so( ADS121X_SELFCAL_CMD);

for (tmp=3D0;tmp