microcontroller programming -- how to begin

IIRC, the 8048 was "optimized" for peripheral controller apps - it seems like you could emulate an 8255 with it, or something. I used one once to do a FIFO, because at the time FIFO chips were astronomical, and nobody knew how to get their hands on one. So, I just dual-ported a 6116 or so, and shuttled bytes through a big ring buffer. :-)

Cheers! Rich

Page 0 on the 6502 is not a set of registers - it is a page of memory which can be accessed with shorter (and therefore faster) addressing modes than the rest of the memory. The 6502 has one general purpose register (the accumulator A), two index registers (X and Y), and a stack pointer, status register and program counter.

But I agree it's a very neat processor - it helped make the BBC one of the fastest and most advanced home micros available in its day. The BBC was significantly faster than the spectrum, even though the 6502 on the BBC ran at 2 MHz (IIRC) on the first systems, and is pure 8-bit, while the Z80A powering the spectrum ran at 3.5 MHZ (again, IIRC) and can do a fair amount of 16-bit arithmetic directly. Part of this was the 6502 (it used fewer clock cycles per instruction than most contemporary processors, and had a pipelined instruction decoder), and part of it was the genius of the Acorn engineers (the same bunch that gave us the ARM). If you want to see some impressive coding, look for a listing of the BBC's MOS rom - to save space, the various tables frequently overlapped with each other and with executable code!

One of my first real assembly programs was for the 6502 - it was a disassembler, running on the BBC micro (actually it was partly assembly, partly Basic).

"David" wrote in message news:448155db$ snipped-for-privacy@news.wineasy.se...

Generally, the 6502 'models', came out in general at about half the clock rate available from the Z80 examples at the same time. The reason was a totally different internal architecture. The Z80, used the clock divided down into four internal phases to perform the instruction fetch, etc.. The

6502, used the two halves of the incoming clock cycle, as it's internal phases. It was a neat architecture, but shows the problems of comparing 'clock rates' when different processors are involved. The same difficulty is true when looking at 'registers. The PIC, is a good example of how complex this can be. It has only a single working register, but has a large register map, built into it's RAM space, some of which function like registers implemented on other processors. For instance, there is effectively an 'index' register, status register etc., all built into the standard memory area. The biggest problem it has though, is a large lack of ability to distinguish these 'core' control registers from the others (such as ones that perform I/O, or are just being used for storage), and no quick ability to save/restore the core 'set' (there is now an ability to automatically save the status, and page select registers, but nothing to do the same for table addressing registers etc.). The difference this makes is major. For example, the Z80 (and several other processors at this time), had a single instruction, allowing it's 'core' set, to be swapped with a second set. This allowed very fast interrupt servicing, with just the call to the handler, swapping of the register set, the actual interrupt code, and a similarly quick return. I wrote a system, which handled synchronous data at over 250000bps, on the Z80 at 6MHz, which was still happily in commercial use until recently. It used the Z80, to feed the data into a dual port memory (implemented using a very early FPGA), and had run for about 20 years, in several hundred sites, without missing a beat. The new replacement, using a modern 'embedded' PC (not my design), needs over 1GHz on the processor clock, to achieve little more, and had major problems on the first few releases, in keeping up with the serial interrupt rate, because of the huge overhead involved with the latter processor when handling interrupts. This can be seen very commonly on the PC, where serial ports in each generation, have needed larger and larger buffers, if data is not to be lost, despite the huge processor clock rates...

There were other nice features to. The two phase clock, allowed you to perform things on memory in the second phase, while the processor accessed the same area in the first. I built one of the commercially available 'second processor' cards for the system, which used this ability. The code, really illustrates the difference, when memory, is a rare commodity, costing a lot per byte, and it is economically worthwhile, to actually 'think' about how best to use it, instead of just shovelling in more memory, which at times seems to be the approach today...

Best Wishes