How to design a programming parallel cable

Hi all! My Xilinx Parallel Cable IV was lost during a travel and it needs 5 weeks to receive another from Memec. I need to program a Xilinx Spartan 3 XC3S400 using Boundary-Scan and Prom programming. It is possible in your opinion to realize such a cable by my own? Someone of you knows where I can find a schematic of such a cable or something explaining the functioning of it? Thanks a lot to everybody Guido

Reply to
Guido
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This is easily possible. There are schematics for the parallel cable III available on the net. You should however additionally put resistors between the input and output of each buffer to provide a hysteresis of a few hundred millivolts. Also, for spartan-3 you must make sure that your series resistors to the fpga are large enough to limit the current to whatever it is the datasheet says. You can not simply supply the buffers with 2.5V because then you will not be able to generate TTL levels for the PC.

Because the original parallel cable III did only work with about 2/3 of all PCs, there are a couple of sites on the net that sell improved and less expensive versions. One that explicitely is Spartan-3 compatible is this one:

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Kolja Sulimma

Reply to
Kolja Sulimma

You can order one from Xilinx's web site. They ship internationally. They got me mine in a couple of days.

Cheers, JonB

Reply to
Jon Beniston

Thank you for your reply. I read that the PROM used in my Spartan3 Board, a XCF02S is full 5V tolerant if supplied with 3.3V (as it is in the board). So in this case it's not strictly necessary to put the series resistors, is it? Another thing...can you tell me where can I found the schematic for the parallel cable III? Thanks a lot Guido

Reply to
Guido

Xilinx's shipping is very good (who ever they use). Ordered on a tuesday night recieved the order on the thursday morning. Not bad from the US to Sydney, Australia.

Alex

Reply to
Alex Gibson

Well, if you do JTAG programming and the FPGA is in the same JTAG chain then the FPGAs TCK and TMS inputs will be driven by the download cable. So you need the series resistors. Also, if the FPGA is behind the PROM in the JTAG chain the TDO pin will be driven to 2.5V by the XC3S. A 5V download cable with CMOS buffers will not recognize this as logic 1. (TTL buffers would)

first hit on google for parallel cable III schematic

also answer #3418 in the xilinx answer database.

Search this newsgroup for more detailed comments by me on how to improve the download cable.

Kolja Sulimma

Reply to
Kolja Sulimma

Thanks to both of you for the reply but as I'm working with a university, in order to order some components I need an estimate and moreover the university can pay with bank transfer only 30 days after the recipt of the goods...so I don't think that i can buy on xilinx web site. Guido

Reply to
Guido

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