looking for a MOSFET

The SOA curve (figure 3) would seem to indicate you're operating outside of the safe area by perhaps 2:1 on the STP20NM50, not taking into account Tj.

Best regards, Spehro Pefhany

Not quite.... The right sloping line in SOA curve (figure 3) corresponds to ~6mJ. The application I am talking about is by no means 60A AND 230V applied for ~1.5us. It is rather ~30A and 120V rectangular pulse equivalent ( I am looking at the oscilloscope picture printout) applied for 1.5us. So, from the pulse energy point of view I should be OK... Thanks Michael Kogan

Not quite.... The right sloping line in SOA curve (figure 3) corresponds to ~6mJ. The application I am talking about is by no means 60A AND 230V applied for ~1.5us. It is rather ~30A and 120V rectangular pulse equivalent ( I am looking at the oscilloscope picture printout) applied for 1.5us. So, from the pulse energy point of view I should be OK... Thanks Michael Kogan

The energy involved is less than the avalanche energy so I think the thermal response curve is the thing to look at, at the edge of the graph at 10us the thermal response is 0.02, (for single pulse) at 1us it looks like its going to be about 0.005 this increases its effective average junction to case thermal resistance by a factor of 200 wich should be ok for

No, that's the easy part. The dissipation occurs in the MOSFET's channel and for short pulses under 25us, the heat can't even make it far into the lead frame, let alone further into any heat sink, so there's no disadvantage at all from using an SMD package.

For a given gate voltage a MOSFET's drain current can be predicted from the datasheet's Typical Output Characteristics or Transfer Characteristics curves. Assuming Vgs = 12V and Vds > 25V, ST's 20nm50 indicates about 45A and IR's 12n25 says 22A. YMWV from part to part. Such currents would result in a 1.2 to 2.5us discharge time. The current would be constant during most of the discharge, except as the junction heats up it'll fall, say up to 35%, as shown by the plots. The dissipated-power plot would show a peak followed by a steady ramp down to zero since P = I V, and V is ramping down.

So we're talking about the FET's silicon rapidly absorbing 5mJ (not 10mJ, since E = 0.5 CV^2), causing a temperature jump in 1us or so, thereafter spreading the heat into the lead frame. The level of the temperature jump will be determined not so much by the peak current or the rapidity of the discharge, as by the junction's thermal mass. Note, a lower current would result in a slower rate-of-rise of the junction temperature, which might improve reliability.

You've no doubt compared your 5mJ discharge energy to the MOSFET's 250 and 650mJ avalanche ratings. But you must keep in mind those are for relatively long pulses, at lower power levels, that spread the heat throughout all of the copper lead frame. Still, they can be an indication the ST part has a larger die and will therefore experience a smaller temperature jump.

IR's Transient Thermal Impedance plot shows about 0.02 C/W at 10us, which we can extrapolate to 0.06 C/W at 1us, using the sqaure-root rule. This translates to 2.5kW for a 150C temperature rise, and 2.5mJ for 1us. ST's Thermal Impedance plot shows a similar value. With a 5mJ 1us pulse both MOSFETs may be experiencing much more than a 150C rise lasting a few us. Speaking of sudden junction- temperature jumps, there's anecdotal evidence that some batches of parts may be less able to withstand such stress than others. That may explain the difference between your IR and ST parts.

If you don't mind a bit slower discharge time, you could lower the current by reducing the gate voltage. This would help your MOSFET survival in two ways: First a lower peak-power level with a slower rate of temperature rise, and Second a longer duration allowing the heat to spread into more of the MOSFET leadframe. You could also add a gate resistor to slow the gate-voltage step. You could also parallel two MOSFETs. Any of these would lead to reduced junction- temperature transients, but together you might get a robust circuit.

Excuse me, I slipped a decimal point. That's 0.006 C/W for 1us, or 25kW lasting 1us for a 150C temperature rise, or 25mJ in 1us. This means a 5mJ 1us pulse in either type of MOSFET should make a 30C step junction-temperature increase. If 5mJ is dissipated over a longer time, say 4us, the rise will be about half or 15C.

The rest of my comments still stand.

Thanks for the comments! I have to apologize - I did not look carefully at the info I had, i.e. I ignored drain to source voltage drop. I have ~1 us wide pulse with less than ~40A average current and less than ~8V average drain-source voltage drop (I missed this part, sorry :o( ).Or less than 240W dissipation for ~1us. These numbers do not even seem to be on the datasheet (Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case). Absorbed energy is 0.24mJ or less - negligible also. In short, I have to figure out why I lost two parts... As to the DPAK - I want to keep it as I do not want to respin the PCB Thanks again! Michael Kogan

Excuse me, how do you discharge a capacitor from 220V, and calculate 8V average? How do you convert absorbing 5mJ of heat into 0.24mJ or less?

Also, it's the instantaneous numbers you have to consider, e.g., 40A * 220V = 8.8kW, not the averages, and it doesn't help to rationalize to smaller values than reality.

The transient power levels are dramatically higher than you seem to realize, and the resulting dT/dt is pretty tough on the MOSFET. However I agree it should be able to handle it. It's possible the problem lies elsewhere, such as excessive voltages arising across wiring inductance, where V = L dI/dt and your dI/dt could easily be 40A/25ns. Note for L = 50nH this means V = 80V. You need to keep wiring L under 5-10nH, not easy, or reduce dI/dt by slowing the gate's risetime. I suggest you consider following some of my suggestions; among these were adding gate resistance and lowering gate voltage.

As I said, with detailed theory, no problem there at all.