MOSFET specs

Actually, never mind, I've misinterpreted Figure 8. It's expressing Rds(on) as a proportion of its value at 25 degrees.

Sylvia.

FWIW: My present "favorite" FET = IRFP4668

Rds = 8.0 mOhm Id = 130 A Vdss = 200 V

Later today, I'm planning to make some SSR's out of these.

Nice, but I do need the high Vdss unfortunately.

Sylvia.

We're designing some SSRs now too. I was looking at FDD86367, 4.2 mohms, 80V, 100A, cheap. The tricky part is protecting them from customer abuse.

We have a simple, cheap, transformer-coupled isolated gate driver circuit, basically a tiny flyback supply. The protection will be a combination of a bit of series resistance and a lot of FPGA code.

I'm also affected by the high reverse recovery charge that MOSFET body diodes seem to have. For example

has a reverse recovery charge of 15uC. In a half-bridge situation, at, say 400V, and switching at 20kHz, if my understanding is correct, that creates a loss of over 100W in the high side switch, which is a lot of heat to get rid of even if it's otherwise acceptable.

Been looking at IGBTs instead.

Sylvia.

A fat body-diode reverse recovery spike can blow out the gate, too.

That, or if you can afford to use low enough Rds(on) that Vds(on) < Vf, you can prevent stored charge by synchronous rectification.

You can also try with a large SiC schottky in parallel, which isn't quite good enough at DC, but will draw current while the body diode is in forward recovery.

Recovery isn't power loss, but it can cause a lot of it. You need some way to deal with it. In the olden days (of SCRs, BJTs and slow diodes), they used saturable reactors to delay switching. Supply inductance is your friend here.

Tim

Yes, a nice low Rds(on) for such a small DPak package. I'm also impressed by the FDMS039N08B in a SOIC-8P package.

Did you take a look at AoE III Fig 3.107, page 205?

Just did.

In fig A, you might replace Q1 and Q2 with a dual optocoupler, and eliminate U2. Like this:

I considered something like that, but the PVs are wimpy, both voltage and average current.

The flyback thing is nice; all the power we could ever want, dirt cheap.

I was going to use some of those self-protecting mosfets, but they have way too much personality. So we're going to measure the voltage across each SSR (which is its own story) and let our FPGA do the protections. I added a wirewound resistor in series with the fets to better define the switch resistance, to limit/measure current, and to take the joules on a fault. We will run a realtime thermal simulation in the FPGA and shut down based on the estimated temperature of the resistor.

I'm fiddling with parts placement.

There are so many concerns (thermals, currents, voltage clearances) it's easier to do one channel myself than explain it to my layout guy. More fun than trekking out to Loews and repairing the deck, too.

What did you use for a transformer, layout looks like a coupled inductor? What's its insulation-voltage rating?

That's why our PV charges a capacitor to 8V, then a pnp npn follower pair for high-gate-current on/off. The ZXTC2061E6TA is a high-current complementary pair in sot-23-6, with beta = 800typ to over 1A. Table 3.5 of MOSFET choices includes FETs with Ciss to 10nF, so 150mA peak momentary drive is good. But I see PVI5033 is rather slow, so your opto-couplers plus a npn/pnp follower pair might be even better.

It's a Bourns SRF0703. It's smaller than the usual DRQ74, and it's rated for 500 volts RMS insulation. The DRQ74 is only spec'd for 200, and actually arcs at 2400.

The totem-pole optocoupler thing can be made a bit faster by boosting the LED side.

We're expecting maybe 50 us on/off with the flyback thing, faster if we waste a bit of power. We don't need speed, except to keep the mosfets out of the bad parts of their SOAR curve.