Logic Question

On 7 Mar., 20:20, Jim Thompson wrote:

somethinglike this?

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-Lasse

I was thinking of the same thing, but it was the TTL 8-bit parity generator (don't remember the number), not the 7486. I think the parity generator/checker used 8 gates.

Apparently Jim doesn't have discreets on his ASIC or he would have liked this.

If it was driven by another like it, as in the parity tree. But couldn't it be driven high and low? (IANAEE)

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Maybe he just did not read this part of the thread. Or I'm blacklisted. The beautiful symmetry should appeal to him.

No, hard driving one input high, the other low would overdrive conducting B-E junctions. And you need to pull the E's low hard to get the output at a logic low level. The base is then driven though the other pull-up.

Now I think of it, this piece or RTL logic with a twist even looks nicer (2x NPN):

|\ VCC A --| >-+------- E C -----+ | |/ | B | (R) \ /--(R)--+ | | X +------+--- OUT / \--(R)--+ | |\ | B | B --| >-+------- E C -----+ |/

A good bottle of dry white signed by Jim is OK to use this :-)

Arie

You missed the part where what I really need is two circuits, each with input A, but one with output A and the other with output Abar, delay to each output EQUAL.

What is your preference in dry white wine ?:-)

Unfortunately I'm on the wagon at the moment. Something untoward going on in my colon. Colonoscopy scheduled for Tuesday. Damned capitalist health care... 1 week delay (from Doctor's order) while I'm weaned from anti-inflammatory which could cause bleeding ;-) ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

      Remember: Once you go over the hill, you pick up speed

A week? It was over a year with the VA.

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You can't fix stupid. You can't even put a Band-Aid? on it, because it's
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"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Could you possibly add a buffer in order to create a 3 stage delay?

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I know. That's a shame :-(

Once upon a time there was the GI Bill where servicemen were properly rewarded for their sacrifices. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

      Remember: Once you go over the hill, you pick up speed

I thought the problem was unequal delays from one input to one output under different conditions (other input is high or low).

This means that David Eather's mux idea is what you need. Since the mux inputs are fixed, the gates can be simplified.

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I am also curious as how that is supposed to work.

If you need an inverted output too just run the bottom mosfet into the base of a top CCS loaded NPN. I.E. a mirror structure to the PNP shown.

(2x

I was just transferred to one of the newest VA clinics in the country, at 'The Villages' which is located south of Ocala, Fl. It has

100 exam rooms, MRI, Catscan, Ultrasound & X-ray. It has a dental clinic, wound care, and optical department. They are supposed to offer Lasik surgery later this year. It has two outpatient ORs, and a dozen other services. The only difference between it and a hospital is that there are no patient rooms. State law sets the number of patient rooms in each area, but has no control over any other services. It also has over 160 parking spaces, compared to the couple dozen at the last clinic I was assigned to. I have lab work there on the 17th, and my first doctor's appointment at the end of the month.

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You can't fix stupid. You can't even put a Band-Aid? on it, because it's
Teflon coated.

The input resistors sum the two inputs to three states, 0 (both 0),

1/2 (either at 1 with the other at 0), or 1 (both 1).

The mosfet gate thresholds are used as comparators for an input state detector. (Both inputs) 0 or 1 turns off either the top or bottom mosfet. 1/2Vcc turns on both.

The output PNP only conducts when both mosfets conduct. I.E.The output goes high when the inputs are either 1-0 or 0-1 but not when 0-0 or

1-1.

couldn't

(2x

Great! Good luck! ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

      Remember: Once you go over the hill, you pick up speed

Thanks. :)

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You can't fix stupid. You can't even put a Band-Aid? on it, because it's
Teflon coated.

I had both ends done a few months ago. Nothing to it.

-----------

Jim Thomps> Great! Good luck!

I had that colonoscopy several years ago. I slept through it.

--
You can't fix stupid. You can't even put a Band-Aid? on it, because it's
Teflon coated.

wrote in

invert

while

xor B

in

=A0 =A0 ...Jim Thompson

=A0 =A0| =A0 =A0mens =A0 =A0 |

=A0 | =A0 =A0 et =A0 =A0 =A0|

=A0|

=A0 =A0 =A0 =A0 |

=A0|

|

Hide quoted text -

=46or some reason that i cannot properly account for, i seem to remember something like true/complement buffers and transmission gates. From an = old copy of the CD4000 series data book of all places IIRC.

josephkk wrote:

similar to what I posted a few days ago?

Version 4 SHEET 1 1356 1108 WIRE 464 -64 -256 -64 WIRE 160 16 -64 16 WIRE 160 32 160 16 WIRE 240 96 240 80 WIRE 272 96 240 96 WIRE 144 160 144 80 WIRE 144 160 -608 160 WIRE 464 224 464 -64 WIRE 464 224 192 224 WIRE 144 256 144 160 WIRE 192 256 192 224 WIRE 240 256 240 96 WIRE -720 304 -784 304 WIRE -720 336 -720 304 WIRE -608 336 -608 160 WIRE -608 336 -720 336 WIRE -576 336 -608 336 WIRE -720 352 -720 336 WIRE 272 384 272 96 WIRE 672 384 272 384 WIRE -288 400 -368 400 WIRE -288 416 -288 400 WIRE -192 416 -288 416 WIRE -64 416 -64 16 WIRE -64 416 -192 416 WIRE -32 416 -64 416 WIRE 160 416 160 304 WIRE 160 416 32 416 WIRE -288 432 -288 416 WIRE -288 544 -288 512 WIRE 160 624 160 416 WIRE 240 688 240 672 WIRE 272 688 272 384 WIRE 272 688 240 688 WIRE 336 688 272 688 WIRE -512 784 -512 336 WIRE 144 784 144 672 WIRE 144 784 -512 784 WIRE 464 816 464 224 WIRE 464 816 192 816 WIRE 144 848 144 784 WIRE 192 848 192 816 WIRE 240 848 240 688 WIRE -64 992 -64 416 WIRE 160 992 160 896 WIRE 160 992 -64 992 FLAG 192 80 0 FLAG -256 16 0 FLAG -288 544 0 FLAG 192 672 0 FLAG 336 752 0 FLAG -720 432 0 FLAG -192 416 input IOPIN -192 416 In FLAG -368 400 input IOPIN -368 400 In FLAG -784 304 control IOPIN -784 304 In FLAG 672 384 output IOPIN 672 384 In SYMBOL nmos4 240 32 R90 SYMATTR InstName M1 SYMBOL pmos4 240 304 M270 SYMATTR InstName M2 SYMBOL Misc\\battery -256 -80 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 1 SYMBOL Misc\\battery -288 416 R0 WINDOW 3 -154 178 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value PULSE(0 1 10u 0 0 5u 10u 50) SYMBOL nmos4 240 624 R90 SYMATTR InstName M5 SYMBOL pmos4 240 896 M270 SYMATTR InstName M6 SYMBOL cap 320 688 R0 SYMATTR InstName C2 SYMATTR Value .1p SYMBOL Misc\\battery -720 336 R0 WINDOW 3 -173 156 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V4 SYMATTR Value PULSE(0 1 10u 0 0 100u 200u 3) SYMBOL Digital\\inv -32 352 R0 SYMATTR InstName A1 SYMBOL Digital\\inv -576 272 R0 SYMATTR InstName A2 TEXT -978 960 Left 0 !.tran 500u

-Lasse